Motorola Corporation

Freescale Semiconductor,inc.

John J Parkes, Jr

James G Mittel

James J Riches

Kai Zhong

Eric Thomas Eaton

Von Alan Mock

Mahibur Rahman

Raul Salvi

John Wayne Simmons

Kevin T McLaughlin

Manbir Nag

A digital tuning system () for changing a cutoff frequency of an analog filter () includes digital synthesizers (and) for producing a two-tone calibration signal () applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (and) for changing the quality factor and arrays (and) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (and) of the filter to each tone (and) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (and) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.

Controlling the bandwidth of an analog filter

A circuit includes a voltage regulator () for outputting a voltage at a regulated level, a protection circuit (), and a load circuit () coupled to the voltage regulator. The protection circuit includes means for preventing the voltage regulator from outputting a voltage at a level higher than the regulated level during a start-up period of the voltage regulator.

High voltage protection for a thin oxide CMOS device

An integrated circuit package () includes a voltage regulator () and a power-out pin () for coupling to a load circuit () via a connection () external to the integrated circuit package and for coupling to an output () of the voltage regulator via a connection (and) internal to the integrated circuit package. The internal connection has a series resistance that causes a voltage drop due to a load current. The voltage regulator compensates for the voltage drop in the internal connection using a current feedback circuit, in which the current fed back is proportional to the voltage drop caused by the series resistance of the internal connection.

Load independent voltage regulator

A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Clock jitter minimization in a continuous time sigma delta analog-to-digital converter

An adaptive analog-to-digital converter (ADC) system () includes an automatic gain control (AGC) controller () for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) () is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC (). The ADC () uses the adjustment signal to dynamically control efficiency of the ADC systemby adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller ().

Signaling dependent adaptive analog-to-digital converter (ADC) system and method of using same

A ring inhibiting charging and discharging circuit (,) for use with an amplification circuit (,) that drives a load (,) is responsive to an input (,) and is capable of generating an output (,) corresponding to the input (,). The ring inhibiting charging and discharging circuit (,) includes a charge element (,) that is responsive to the output (,) from the amplification circuit (,). The charge element (,) is capable of charging the load when the input voltage is greater than a preselected multiple of the output voltage. A discharge circuit (,) is responsive to the output (,) from the amplification circuit (,) and includes a feedback circuit (,) and a staging circuit (,). The feedback circuit (,) asserts a difference signal when the output voltage is less than the preselected multiple of the input voltage. The staging circuit (,) is responsive to difference signal and gradually reduces the rate at which the load (,) is discharged over a preselected period of time once the difference signal indicates that the output voltage is within a preselected range of the input voltage.

High capacitance drive fast slewing amplifier

A voltage regulator circuit (100) for coupling to a power supply voltage (BPLUS) generates and regulates an output voltage (VREG). The voltage regulator circuit (100) includes a gain control element (148) for controlling the loop gain of the voltage regulator circuit (100) in response to the output current. Under heavy load conditions, the gain control element (148) functions to reduce (716) the output voltage (VREG) and thus the output current of the voltage regulator circuit (100) to avoid an overload that would pull the power supply voltage (BPLUS) below a predetermined level.

Voltage regulator circuit having adaptive loop gain

A method for battery saving in a battery powered radio communication device having a receiver for receiving a radio frequency (RF) signal comprises the step of enabling (100) the receiver for reception of the RF signal. The method further comprises the steps of determining (120) that the RF signal is being received at an off-signal data rate different from an on-signal data rate at which data is normally provided to the battery powered radio communication device and disabling (130) the receiver in response to determining that the RF signal is being received at the off-signal data rate.

Method and apparatus for battery saving in a radio communication device

A low-voltage IF amplifier (112) provides automatic gain control (AGC) of a source amplifier (104) supplying an IF input signal to the IF amplifier (112). The IF amplifier (112) includes cascaded amplifier stages (202) that include an amplifier element (344) having an input (122) for receiving a stage input signal, and an output (124) for generating an amplified stage output signal in response. The amplifier stages (202) also include a received signal strength detector (346), or RSSD, for generating a gain control current responsive to the stage input signal. The IF amplifier (112) also includes a current summer (206) for summing the gain control currents generated by the RSSDs (346) to produce a total gain control current, and a gain control element (204) that controls the gain of the source amplifier (104) in response to the total gain control current, such that signal levels within the source amplifier (104) are maintained within a linear operating range.

Low-voltage intermediate frequency amplifier providing automatic gain

A display device (20) comprises a display (21) for displaying information and an electroluminescent panel (22) located contiguous to the display for sensing ambient light and lighting the display when the ambient light is below a threshold.

Combination display backlight and light sensor

A filter (13) for providing temperature compensation for the quality factor thereof comprises transconductance amplifiers (23 and 24) in a gyrator configuration coupled between an input node (21) and an output node (22). A parallel capacitor (25) is coupled between the input node (21) and a supply voltage, and a parallel resistor (26) is coupled between the input node (21) and the supply voltage. A series capacitor (27) is coupled to the output node (22), and a series resistor (28) is coupled between the second capacitor (27) and the supply voltage.

Growing community of inventors

Boynton Beach, FL, United States of America

John J Parkes, Jr