International Business Machines Corporation

John J Moser, Jr

John E Gersbach

Ernest H Millham

John James Shushereba

Gary P Visco

Apparatus for applying for a plurality of test cycles data specifying a plurality of test conditions to a multiple pin electronic circuit. A random access memory includes at a plurality of higher order addresses a complete data field for a plurality of test cycles. Some of said data fields include an operational code indicating that a minority of data bits in a field are to change in a consecutive number of following test cycles. A hold register is connected to receive each addressed row of test data from the memory. The higher order addresses of a memory addressed to produce complete data fields in the hold register. An operational code will be decoded to indicate a number of subsequent consecutive test cycles where a minority of data in the hold register are to be changed. The lower order addresses of the memory are subsequently addressed for a number of consecutive test cycles indicated by the operational code. The data contained in the lower order memory addresses is inserted in the hold register without changing the contents of a majority of hold register data bits.

Apparatus for reducing test data storage requirements for high speed

This teaches that logic circuits such as Cascode circuits can be D.C. tested for normally untestable defects, such as emitter shorts or collector opens, by applying to the output of the circuit, or portion of the circuit, under test an additional voltage though an impedance. The specific embodiment teaches a resistor and diode in series as the impedence.

Imbalance circuits for DC testing

This describes a tristate driver circuit designed such that it will not be destroyed by excessive high voltage conditions when two such drivers are connected to a bus at the same time. The circuit accomplishes this with parallel high current, low impedance and low current, high impedance output devices, coupled to means for causing the high current, low impedance devices to supply, to the circuit output, only the initial high currents required without inhibiting the low current, high impedance devices from maintaining the steady state conditions needed to clamp the output at the desired output level. The circuit is arranged to cause both high and low current output devices to be initially conductive to charge the output terminal to the desired level, but to subsequently shut off the high current, low impedance device while keeping the low current, high impedance device in a condition to clamp the output at the desired level. This result is achieved by providing the high current output devices with means for automatically terminating once the initially required high current has been supplied to the output.

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Essex Junction, VT, United States of America

John J Moser, Jr