International Business Machines Corporation

John J Ellison

Joseph L Temple, Iii

Chon Cheong Lei

Michael Gerard Nealon

Dennis Felix Clocher

Joseph John Lisowski

Jorge L Rivera

A system for testing every one of the signal inputs and outputs (I/O) of a fine pitch multi-chip semiconductor module utilizing a selective netlist, through the intermediary of presently available test equipment. More particularly, the system facilitates the testing of fine pitch multi-chip modules utilizing 1.0 mm ceramic column grid array (CCGA) technology in order to facilitate the use of increased system interconnect capabilities. Additionally, there is provided a method of employing a selective netlist in order to test fine pitch multi-chip semiconductor modules; especially such as, but not limited to 1.0 mm pitch ceramic column grid array (CCGA) modules by employing commercially available test equipment.

Selective netlist to test fine pitch multi-chip semiconductor

A pre-production, prototype multi-chip module adapted for preliminary performance timing and functional tests includes a plurality of chips attached to a substrate. Multiple nets are embedded within the substrate connecting the chips. A layer over the substrate encapsulates the chips. Production input/output pins on the substrate are connected to the chips. An area on the upper surface of the module is not covered by the encapsulating layer, which contains upper pads adapted for connection of a second module containing spare circuits to the substrate, wherein the upper pads are connected to the at least one net. Some of the upper pads have connections to each other near the surface of the encapsulating layer, wherein the connections are adapted to be severed for connecting a second module containing spare circuits to one or more of the chips.

Prototyping multichip module

Growing community of inventors

Elizaville, NY, United States of America

John J Ellison