Hewlett-packard Company

Agilent Technologies, Inc.

John J Corcoran

Samuel H Maslak

Travis N Blalock

Thomas Hornak

Thomas Allen Knotts

Kenneth D Poulton

Paul J Vande Voorde

Neela B Gaddis

An apparatus and a method for protecting charge storage elements from photo-induced currents in silicon integrated circuits are provided. In order to protect against photo-induced currents that are generated outside the storage node circuits themselves, an n-well guard ring is placed as closely as possible to the transistors and other elements in the storage node circuits. As a result there is a minimum of exposed silicon area in which light can produce current in areas next to the storage node circuits, and the n-well guard ring captures photo-induced currents that are generated outside the storage node circuits. In order to protect against the photo-induced currents that are generated inside the storage node circuits, an aluminum interconnect layer is placed on top of the storage node circuit, separated by an insulating layer of silicon dioxide. This creates a shield against the light and protects the storage node circuit by reflecting light away.

Apparatus and method for protecting integrated circuit charge storage elements from photo-induced currents

Methods for calibrating a plurality of N time-interleaved analog-to-digital converters (ADCs) for any integer N.gtoreq.2 by detecting and/or correcting timing and amplitude errors therein, where each of the ADCs, numbered j=1, 2, . . . , N has an identical clock frequency f.sub.c and period T.sub.c =(f.sub.c).sup.-1. Ideally, the N ADCs are clocked uniformly in time so that two consecutively clocked ADCs number j1 and j1+1 have effective sampling times that differ by time intervals of uniform length .DELTA.t=T.sub.c /N. Ideally, the N ADCs also have identical gains from their analog input signals to their digital output signals. In a calibration procedure, all ADCs receive a common analog input signal S.sub.in (t)=Asin[2 .pi.(1+s)f.sub.c t], where s is a non-zero fractional number satisfying -0.5&lt;s&lt;0.5. The output signal values from ADC number j provide a set of ordered pairs of values (t.sub.i, D.sub.ij) for sampling times t.sub.i, and the set of values {D.sub.ij }.sub.i with j fixed is approximated by another set of values { V.sub.ij =A.sub.j sin[2 .pi.sf.sub.c t.sub.i +.phi..sub.j ]}.sub.i. Here, the amplitudes A.sub.j and phase angles .phi..sub.j are chosen to provide a best numerical fit to the set {D.sub.ij }.sub.i for each j=1, 2, . . . , N, according to some criterion. The phase differences .DELTA..phi..sub.j2,j1 =.phi..sub.j2 -.phi..sub.j1 are then determined and compared with the ideal phase difference value .DELTA..PHI..sub.j2,j1 =2 .pi.(j2-j1)/N to determine if a relative timing error exists between ADCs number j1 and j2. In a similar manner, the amplitude differences A.sub.j2 -A.sub.j1 are compared to determine if a relative gain error exists between ADCs number j1 and j2.

Timing and amplitude error estimation for time-interleaved

Apparatus for introduction of a controllable time delay in the transition of a logic device output signal from a first logical level to a second logical level, in response to change of an input signal, or the difference of two input signals from a third logical level to a fourth logical level, delivered to the logic device. In a first embodiment, a limiting amplifier receives an input signal S.sub.in and a threshold signal V.sub.T at its two terminals and forms an amplified difference output signal S.sub.out. A selected voltage level signal V.sub.L and S.sub.out are received at a signum function module and the output signal sgn(S.sub.out -V.sub.L) is formed and issued. The signum output signal is multiplied by a controllable real number m and is added to V.sub.L to form the threshold signal V.sub.T. The desired output signal S.sub.out makes a transition between the first and second logical levels, with a time delay that is controllable by choice of the number m. In a second embodiment, which also uses a signum function, two input signals, S.sub.in,1 and S.sub.in,2, give rise to two output signals, S.sub.out,1 and S.sub.out,2, and the difference signal S.sub.out,1 -S.sub.out,2 makes a transition between two logical levels with a time delay that depends controllably on choice of the number m.

Logic gates with controllable time delay

A system is provided in which an analog storage device stores, delays, and/or changes the time scale of an input analog waveform. The system provides an output which is corrected for the gain and offset of the analog storage device by exercising the system using known analog inputs and combining the output so obtained with the uncorrected output of the input analog waveform. In a preferred embodiment, the output is also corrected for non-linear and dispersive distortion of the storage device by exercising the system using an input analog signal derived from the earlier output of the system (corrected for gain and offset) and suitably combining the new output so generated with the earlier output.

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Portola Valley, CA, United States of America

John J Corcoran