Compagnie Honeywell Bull

Honeywell Information Systems Inc.

Compagnie Internationale Pour L'informatique Cii-honeywell Bull

John J Bradley

Benjamin S Franklin

Marc Michel Appell

Philippe-Hubert deRivet

Patrick Dufond

Jacques Michel Bienvenu

Jean-Claude Marcel Cassonnet

Claude Carre

Henri Verdier

Jean-Louis Bogaert

Duc L Tuong

Philippe-Hubert De Rivet

Georges Lepicard

Duc Luu

David M Slosberg

Claude Massuard

Philippe D De Sabatier

An apparatus for enabling communication of information between processes being carried out on a computing system. Each process is assigned a control block including a specialized memory element. A process being executed modifies the state of each memory element if it discovers any information of interest to processes awaiting execution. Before the next process is executed, the memory element in its control block is tested to find out if the previously-executed process left any information of interest.

Apparatus and method for communication of information between processes

A method of and apparatus for executing a family of instructions provides synchronization of processes in a multiprocessing system. Representations of processes awaiting data (information units) such as the completion of an asynchronous operation or the availability of a resource are stored in a memory in a first queue and representations of information units available to processes are stored in memory in a second queue. Transfer of information units between processes is controlled by data elements known as 'semaphores' stored in the memory. Each semaphore contains a field having a numerical value identifying which of the two different kinds of queues is present. When a P instruction is executed by a process indicating that the process requires data in order to continue operating or a V instruction is executed indicating that an information unit is available for transfer to another process, a semaphore is addresses and its field tested to determine whether processes or information units are available to enable the information transfer between processes to be effected. Once the information transfer is completed, the field of the addressed semaphore is up-dated.

Apparatus and method for transferring information units between

An information structure, or semaphore, serves as a signalling mechanism in process synchronization to connect a process and a non-simultaneously occurring event or resource. The semaphore is a data structure which stores representations of processes awaiting particular events or alternatively stores representations of events awaiting processes. Semaphore data structures are developed in two storage areas. First and second groups of process links are stored in the first storage area to establish, respectively, a first queue of processes ready to operate and a second queue, associated with the semaphore structure, of processes awaiting occurrences of a first particular event prior to being ready to operate. In the second storage area are stored first and second groups of message links to establish respectively a first queue, associated with a semaphore structure, representing second particular events and a second queue of unused links. A signal is generated in response to operation of a first process to denote the occurrence of a first event. In response to the signal, the first event is associated with a process represented by a process link in the second queue of process links when the first event is the first particular event. When no queue has a process link identifying a process awaiting the occurrence of the first event, a representation of the first event occurrence is stored in a message link of the second queue of message links to be transferred to the first queue of message links. Process and event occurrence representations are thus transferred among the process and event queues during synchronization that takes place between the processes and events.

Apparatus and method for providing synchronization between processes and

Firmware is provided to change, upon execution, information in the system base which is located in both main memory and internal scratch pad registers. Hardware structures controlled by a microprogrammed control store, which provides for the generation of signals causing the creation of an image in main memory of a communication center comprised of registers at another location in the central processing unit. The microprogrammed control store further generates signals which causes the interchange of the information between the communication center and its image.

Switch system base mechanism

Apparatus in a data processing system to initialize a semaphore held in a memory field of the data processing system or, alternatively, to restore the semaphore to a previous predetermined state. A count field, or tally field, provided in the semaphore is initialized by a particular instruction. The semaphore can be either a non-message semaphore or a message semaphore. The instruction initializes the semaphore count field of a non message semaphore to zero or a preloaded positive value. For a message semaphore, this instruction initializes the count field to zero. If the message semaphore previously had a positive count, the messages tied to the semaphore are released and the message links holding the messages are transferred to a free message link queue tied to the free link semaphore in the same semaphore descriptor segment. The apparatus includes a retrieving member for reading the content of the semaphore in the memory of the data processing system, a testing member for testing the count field of the semaphore for generating a first signal when the count field represents the number of processes in queue and a second signal when the count field represents the number of times a particular kind of event has occurred, a changing unit responsive to the second signal and controlled by the particular instruction for changing the number inside the count field to a predetermined number and a control member responsive to the first signal and controlled by the particular instruction for controlling the data processing system to cease execution of the particular instruction and to begin to execute a different instruction.

Apparatus and method for semaphore initialization in a multiprocessing

A procedure call mechanism implemented by hardware instructions and a hardware recognizable mechanism known as a stack. A procedure call is utilized by users who have written their programs in a modular way to pass from one program module to another, it is used by user programs to avail themselves of operating system services, and it is used by the operating system itself to achieve a responsive modular structure. The stack is a mechanism permitting the above to be done. A stack is a segment of memory and comprises a number of contiguous portions, known as stack-frames, which are accessed in last in, first out LIFO fashion. Each procedure call creates a stack frame, with subsequent procedure calls creating new stack frames; each exit deletes stack frames thus 'popping up' a previous stack-frame. Thus a history of calls is correctly maintained in order to allow a return.

Call and stack mechanism for procedures executing in different rings

Computer data and procedure protection by preventing processes from intering with each other or sharing each other's address space in an unauthorized manner is accomplished in hardware/firmware by restricting addressability to a segmented memory and by a ring protection mechanism. To protect information in segments shared by several processes from misuse by one of these processes a ring protection hardware system is utilized. There are four ring classes numbered 0 through 3. Each ring represents a level of system privilege with level 0 (the innermost ring) having the most privilege and level 3 (the outermost ring) the least. Every procedure in the system has a minimum and a maximum execute ring number assigned to it which specifies who may legally call the procedure. Also maximum write and read ring numbers specify the maximum ring numbers for which a write and/or read operation is permitted. Processes use a segmented address during execution wherein segment tables isolate the address space of the various processes in the system. Hardware checks that the address used by a process is part of the address space assigned to the process, and if the address is outside the prescribed address space, an exception occurs. A process cannot refer to data within the address space of another process because the hardware uses the segment table of the referencing process.

Protection of data in an information multiprocessing system by

A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows: 1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU); 2. ready -- the process is ready to run as soon as it is given control of the CPU; 3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state; 4. Suspended -- the process has been temporarily stopped (from a source external to the process). The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Process management structures and hardware/firmware control

A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an 'ear' are as follows: A. when the process state switches from a running state to a waiting state; or B. when the process state switches from a running state to a suspended state. In both instances the CPU is given away and replaced by the PCB.

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Garches, France

John J Bradley