International Business Machines Corporation

Globalfoundries Inc.

Other

John J Benoit

Qizhi Liu

Peter B Gray

James Randall Elliott

Alvin Jose Joseph

Christa Regina Willets

Anthony K Stamper

Vibhor Jain

Robert Mark Rassel

Xuefeng Liu

James Albert Slinkman

Natalie Barbara Feilchenfeld

Stephen Arthur St Onge

David S Collins

Panglijen Candra

Mattias E Dahlstrom

Peng Cheng

Michael Lawrence Gautsch

Mark D Dupuis

Blaine Jeffrey Gross

John R Long

James R Elliot

A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal.

In-line measurement of transistor device cut-off frequency

Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

Bipolar junction transistors with self-aligned terminals

Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Cand collector resistance Rare both minimized.

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region

A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.

Bipolar transistor structure and method including emitter-base interface impurity

A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

Optimized device isolation

An extremely reliable, easily portable perimeter alarm system. It is comprised of a light beam controlled radio transmitter and personal warning devices capable of individually warning preoccupied highway workers of the imminent danger present when an errant vehicle violates the established perimeter of a work site. This warning will allow the workers to take evasive action and potentially avoid injury and/or death. It is also the object of this invention to allow for an extremely reliable, easily portable perimeter penetration alarm system that can be utilized in other appropriate settings by security guards, military personnel, etc., and which would provide for confidential notification to such personnel that a temporarily established portable perimeter line had been violated.

Portable personal electronic perimeter alarm

Growing community of inventors

Williston, VT, United States of America

John J Benoit