Gennum Corporation

Semtech Canada Corporation

John Hudson

Ryan Eckhardt

Stephen Paul Webster

Mohammad Hossein Shakiba

Eliyahu D Zamir

Nigel Seth-Smith

David L Lynch

Aapoolcoyuz Biman

Jack MacDougall

Martin Rofheart

Gareth M Heywood

Dwayne G Johnson

Birubi Ram Biman

Jack Macdougall

Mahammad H Shakiba

Jack Mcdougall

A video processing system may include: a video deserializer having (i) an input for receiving a serial data stream containing video data and (ii) a serial to pseudo-parallel converter, coupled to the serial data stream, for generating from the serial data stream a plurality of serial data output streams through a plurality of serial output lanes; a video serializer having (i) a plurality of inputs for receiving serial data streams and (ii) a pseudo-parallel to serial converter, coupled to the plurality of input serial data streams, for generating a single serial data stream from the plurality of input serial data streams; and a programmable video processing device, coupled to the video deserializer and the video serializer, and having a plurality of interface pins for receiving the plurality of serial output lanes from the deserializer and for transmitting the plurality of serial data streams to the serializer.

Video serializer/deserializer having selectable multi-lane serial interface

A crosspoint selector switch for simultaneously supporting multiple data formats having different switch reconfiguration timing requirements, comprising; a configurable switch section for selectively connecting outputs thereof to receive data from respective inputs thereof in response to operational switch data; and a configuration section operatively connected to provide the operational switch data to the switch section, the configuration section storing switch configuration data supporting multiple different configurations of the switch section, the configuration section being operative to receive different operational update commands each associated with a different configuration for the switch section and update the operational switch data from the stored switch configuration data to reconfigure the switch section in dependence on which of the different operational update commands is received.

Crosspoint switch for use in video and other applications

Systems and methods are provided herein for interfacing a first multi-media digital device with a second multi-media digital device. An exemplary method includes the steps of: (i) converting a plurality of differential digital content channels from the first multi-media digital device into a plurality of single-ended digital content channels; (ii) transmitting the plurality of single-ended digital content channels from the first multi-media digital device to the second multi-media digital device via one or more coaxial cables; and (iii) receiving the single-ended digital content channels from the one or more coaxial cables and converting the single-ended digital content channels back into a plurality of differential digital content channels that are supplied to the second multi-media digital device. Additional steps of the exemplary method may include: (i) transmitting one or more auxiliary channels between the first multi-media digital device and the second multi-media digital device; and (ii) combining the one or more auxiliary channels with at least one of the plurality of digital content channels to form a combined channel to be transmitted from the first multi-media digital device to the second multi-media digital device.

Multi-media digital interface systems and methods

A video processing system may include a video deserializer, a video serializer and a programmable video processing device. The video deserializer may have an input for receiving a serial data stream containing video data and a serial to pseudo-parallel converter, coupled to the serial data stream, for generating a plurality of serial output lanes from the serial data stream. The video serializer may have a plurality of inputs for receiving serial data streams and a pseudo-parallel to serial converter, coupled to the plurality of input serial data streams, for generating a single serial data stream from the plurality of input serial data streams. The programmable video processing device may be coupled to the video deserializer and the video serializer, and may have a plurality of interface pins for receiving the plurality of serial output lanes from the deserializer and for transmitting the plurality of serial data streams to the serializer.

Systems and methods are provided herein for interfacing a first digital device with a second digital device. An exemplary method includes the steps of combining one of a plurality of digital content channels and a back channel to form a composite channel, the back channel for transmitting information from the second multi-media digital device to the first multi-media digital device, converting a digital content channel and the composite channel from the first digital device into a plurality of single-ended digital content channels, transporting the plurality of single-ended digital content channels from the first digital device to the second digital device, and converting the single-ended digital content channels back into the digital content channel and the composite channel that are supplied to the second digital device. Cross-talk interference is reduced between the back channel and one of the plurality of digital content channels via a cross-talk cancellation filter.

Transmit, receive, and cross-talk cancellation filters for back channelling

A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

System and method for processing digital visual interface communication data signals and display data channel communication signals over a transmission line

A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC  extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

An auto-configurable video deserializer with embedded audio support includes a video core, a clock generator and an audio core. The video core receives a serial video signal of an unknown video standard, converts the serial video signal into a parallel video signal, and decodes the parallel video signal to identify the unknown video standard and generate one or more auto-configuration signals. The clock generator generates an audio clock signal. The audio core is coupled to the video core and the clock generator, and receives the parallel video signal and one or more auto-configuration signals from the video core and receives the audio clock signal from the clock generator. The audio core uses the auto-configuration signal(s) to automatically locate and extract audio data from within ancillary space of the parallel video signal and synchronizes the extracted audio data with the audio clock signal to generate an audio output signal.

Video serializer/deserializer with embedded audio support

A video processing system and method are provided for generating clock and timing signals from an incoming video signal. The system includes a timing reference circuit for generating a reference clock signal, a video format detector coupled to the reference clock signal and to synchronization data derived from the incoming video signal for generating a format signal indicating the format of the incoming video signal, and a clock and timing generator circuit coupled to the format signal and the reference clock signal for generating clock and timing signals that emulate the incoming video signal, and may be locked to the incoming video signal.

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Burlington, Canada

John Hudson