Texas Instruments Corporation

John Howard MacPeak

Freidoon Mehrad

Eddie Hearl Breashears

Douglas Edward Shelton

Douglas Ticknor Grider

Xiangzheng Bo

Douglas Tad Grider, Iii

Bruce Lynn Pickelsimer

Paul A Schneider

John Frederic Schreck

David J McElroy

Brian Keith Kirkpatrick

George R Misium

Stephen Keith Heinrich-Barna

Xiang-Zheng Bo

Debra J Dolby

Aswin N Mehta

Clyde F Dunn

A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs

A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.

Split gate memory cell fabrication and system

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

Partially disposed gate layer into the trenches

A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.

Select gate self-aligned patterning in split-gate flash memory cell

A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.

Adaptive programming for flash memories

An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided.

Programming of memory cells in a nonvolatile memory using an active transition control

An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate transistors with control gates coupled to corresponding word lines, and drain electrodes coupled to corresponding bit lines. A memory cell is programmed by applying a high programming voltage to its control gate along with applying a high programming voltage to its drain. Multiple memory cells within a row can be programmed by applying the programming voltage to the word line of that row, during which multiple bit lines receive their programming voltage, without removing the word line programming voltage when changing the programming from one bit line to another.

Ripple programming of memory cells in a nonvolatile memory

A method is described for forming a memory structure using a hardmask ( ). The hardmask ( ) protects the second polysilicon layer ( ) during a SAS etch process. In addition, sidewall structures ( ) are formed which protect the inter-polysilicon dielectric layer ( ) during the hardmask ( ) etch process.

Flash memory cell process using a hardmask

A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate stack (,) is formed on an insulating region (,) of a semiconductor substrate. The control gate (,) is removed from the gate stack (,) and electric contacts (,), (,) are formed to contact the floating gate (,) to form the resistor.

Method to fabricate a semiconductor resistor in embedded flash memory application

A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for 'ones' at low control gate voltage Vcc and for 'zeros' at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.

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Garland, TX, United States of America

John Howard MacPeak