Lam Research Corporation

John Hoang

Meihua Shen

Thorsten B Lill

Hui-Jung Wu

Baosuo Zhou

Nagraj Shankar

Jialing Yang

Prithu Sharma

James Samuel Sims

Gowri Kamarthy

Andrew John McKerrow

Alexander Dulkin

Kathryn Merced Kelchner

Shane Tang

Thomas Joseph Knisley

Vikrant Rai

Danna Qian

Gereng Gunawan

Bart Jan Van Schravendijk

Harmeet Singh

Yang Pan

Mark Naoshi Kawaguchi

Ji Zhu

Yoshie Kimura

Ananda K Banerji

Monica Titus

Yifeng Zhou

Kevin M McLaughlin

Shuogang Huang

Nathan Musselwhite

Jay E Uglow

Hao Chi

Aaron Lynn Routzahn

Nicholas Dominic Altieri

Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon.

Film stack simplification for high aspect ratio patterning and vertical scaling

Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.

Conformal damage-free encapsulation of chalcogenide materials

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

Self-aligned vertical integration of three-terminal memory devices

Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H, CH, CF, NF, and Cl. Boron-containing halide gases include BCl, BBr, BF, and BI. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles.

Cobalt etch back

Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Liner and barrier applications for subtractive metal integration

A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber

A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed Hcontaining gas and providing a pulsed halogen containing gas, wherein the pulsed Hcontaining gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed Hcontaining gas has an Hhigh flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the Hhigh flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.

Method to etch copper barrier film

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Fremont, CA, United States of America

John Hoang