Digital Equipment Corporation

Digital Equipment Corp., Patent Law Group

3com Ireland

John Hickey

Anne G O'Connell

Tadhg Creedon

Eugene O'Neill

William Paul Sherer

Vincent Gavin

Eugene G O'Neil

Richard Gahan

John Byrne

Apparatus for controlling data flow using lookup tables to link incoming

An implementation efficient interrupt select mechanism which allocates interrupt flags between N interrupt requestors, e.g. communication channels. A multi-channel controller provides the select mechanism with control signals and asserts an interrupt request when a channel, being visited by a scanner, which may be incorporated into the controller, is asserting an interrupt request. If the interrupt flag is available, the number of the channel asserting the request is locked into a latch. The latch remains locked until the interrupt request is cleared, a control signal is received from the controller and the channel being visited by the scanner equals the channel number stored in the latch. The scanner increments from channel to channel regardless of the assertion of the interrupt flag or the locking of the latch. In this manner, a single scanner may be used with any number or interrupt select mechanisms.

Implementation efficient interrupt select mechanism

Two devices HR and FR are coupled to a bus with a common memory via a port controller. Device HR requires a high (or maximum) average rate of access, device FR requires a fast response (minimum latency) in establishing access. Request signals HRQ, FRQ from the devices are latched by latches 20 and 21, passed as HRX, FRX through an arbitration or resolver circuit 22 as HRY, FRY to a sequence control unit 23 to initiate an access cycle. Cycle timing is determined by a delay line timebase circuit 24, which responds to a single change of level of a signal DLY (in either direction). Latch 21, when set, generates an request pending signal FRRP which is fed to the HR device to cause it to increase its cycle length so that the FR access cycle will finish before the next HR access cycle is initiated.

Port controller

Loop-back detection and signalling is achieved on any DS-0 channel that conforms to 56 kbps operation such as DDS in a DS-1 digital data transmission system. A standard DS-1 chip set (line interface unit, framer, and link layer controller) is used, coupled to 24 transmit and receive buffer means in the customer main memory. The framer detects control bits by using Channel Associate Signalling, (designed for digitising voice in-band signalling and not normally used for data transmission), in the incoming signal and interrupts the customer CPU, which determines from the framer which channel caused the interrupt, changes the mode of the relevant channel, checks that channel's receive buffer means for loop-back codes, and, if enough successive loop-back codes are found, copies the receive buffer means into the transmit buffer means (with code mapping) for as long as the loop-back condition exists.

DS-0 loop-back detection on a DS-1 line

Growing community of inventors

Galway, Ireland

John Hickey