4198638 Canada Inc.

Hyperchip Inc.

419638 Canada Inc.

John Haughey

Richard S Norman

Marcelo De Maria

Sébastien Côté

Carl Langlois

Yves Boudreault

Methods and apparatus for processing a plurality of sets of routing information received from corresponding ones of a plurality of neighbor nodes connectable to a router, the router having a plurality of memory units accessible via separate paths. The method comprises creating a respective plurality of non-identical routing information subsets from each of at least one of the received sets of routing information; accessing the plurality of memory units via the separate access paths; and storing the plurality of non-identical routing information subsets created from a given one of said received sets of routing information in respective ones of the plurality of memory units. By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Methods and apparatus for storage and processing of routing information

A method, system and computer readable storage medium for executing a set of tasks. The method includes selecting an incomplete task in the set and then either starting its execution (if it was not previously suspended) or resuming its execution (if it was previously suspended). An execution timer is also started. If the selected task completes before expiry of the execution timer, the selection process is reinitiated; otherwise, the selected task is suspended, and the selection process is reinitiated. In this way, processing of a lengthy or lower-priority task can be pre-empted by processing of a shorter or higher-priority task. The method may also involve recognizing that a new version of an existing task already in the task set has been added thereto. In such a case, the older version is removed from the task set even if it is not yet complete.

Method and system for executing multiple tasks in a task set

A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.

Cell-based switch fabric with distributed scheduling

Method, apparatus and software for processing sets of routing information in a router having a plurality of memory units accessible via separate access paths. The sets of routing information are typically routes received from neighbour nodes. The method includes creating a plurality of non-identical routing information subsets from each received set of routing information, accessing the memory units via the separate access paths and storing the routing information subsets created from a common set of routing information in respective ones of the plurality of memory units, By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units. In addition, the present invention discloses embodiments which distribute computational complexity among multiple processing units in communication with the plurality of memory units, thereby allowing computation of output routing information bases and forwarding tables to occur in parallel.

A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of the array selected on a basis of the determined destination. Each cell further includes a plurality of receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets to the I/O interface. In this way, the transmitter in a given cell functionally extends into those cells where dedicated receivers are located, reducing transmitter memory requirements and allowing the switch fabric to be implemented on a single chip.

Cell-based switch fabric architecture implemented on a single chip

A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, permitting an exchange of data packets between the cells of the array and an exchange of control information between the cells of the array. Each cell is operative to control transmission of data packets to other cells of the array at least in part on a basis of the control information. The control information is thus used to regulate the flow of data packets between cells.

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Richford, VT, United States of America

John Haughey