Intel Corporation

John Harper

Malavarayan Sankarasubramanian

Nachiket R Raravikar

Mitul Bharat Modi

Carl L Deppisch

Pramod Malatkar

Christopher D Combs

Steven A Klein

Patrick Nardi

Bamidele Daniel Falola

Shenavia S Howell

Susmriti Das Mahapatra

Xiao Lu

Jieping Zhang

Alexander W Huettis

Valery Ouvarov-Bancalero

Ravi Siddappa

James Mertens

Jiongxin Lu

Mohit Sood

A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an 'anti-invar' metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa.

Integrated circuit die package stiffeners of metal alloys having exceptionally high CTE

An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

Chip-scale package architectures containing a die back side metal and a solder thermal interface material

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

Varied ball ball-grid-array (BGA) packages

Growing community of inventors

Chandler, AZ, United States of America

John Harper