Motorola Corporation

Other

John H Quigley

James S Caravella

Jeremy Charles Smith

David A Newman

David F Mietus

Gary W Hoshizaki

Percy V Gilbert

Shih W Sun

Ben Gilsdorf

James S Carvella

An ESD protection circuit (,) includes a low capacitance diode (,), a voltage divider, a trigger transistor (,), and an SCR. Reducing the capacitance associated with the diode (,) makes the ESD protection circuit particularly suitable for RF applications. To form a low capacitance diode, the parasitic junction capacitance of the diode (,) is hidden in a like-doped well; for example, an N&plus; cathode (,) of the diode (,) may be folded or formed partially in an N-well (,). Because the N-well (,) does not form a junction with the N&plus; cathode, the junction capacitance associated with the portion of the N&plus; well lying inside the N-well is hidden or canceled by the N-well (,), thereby reducing the overall capacitance of the diode (,).

Electrostatic discharge protection circuit for an integrated circuit and method of manufacturing

A circuit and method produce a pump current (I.sub.p) at the output (31) of a charge pump (26). A switching transistor (32, 35) is coupled at a node (38, 39) to a current source transistor (33, 34) to produce the pump current at a specified magnitude in response to an input pulse (V.sub.PU, V.sub.PD). A charge is stored on a parasitic capacitance of the node. A charge conduction path (42, 43) is coupled to the node and enabled on one transition edge of the input pulse to alter the charge by routing to a discharge node (45) to reduce charge flowing to the output as an error current. The charge conduction path is disabled on the other transition edge of the input pulse to isolate the node from the output.

Charge pump circuit and method

A non-breakdown triggered electrostatic discharge (ESD) protection circuit (11) having a voltage divider circuit and a SCR (22) protects an integrated circuit from an ESD event. The voltage divider includes a capacitor (17) and a resistor (18). The voltage divider connects to a pad of an integrated circuit and generates a trigger voltage for enabling the SCR (22) when an ESD event is applied to the pad. A worst case ESD voltage transient is used to calculate a trigger voltage for the SCR (22). The trigger voltage is selected at a voltage below where damage to the integrated circuit occurs. The SCR (22) is designed to have a turn on time constant that prevents normal signal levels from triggering the SCR (22).

Non-breakdown triggered electrostatic discharge protection circuit for

A thin film silicon on insulator circuit with a low voltage triggered, surface silicon controlled rectifier (30) for electrostatic damage protection and method is provided. A surface silicon controller rectifier (30) is formed in a thin device layer (130), overlying a buried insulation layer (110) and electrically coupled to a low voltage trigger apparatus (36). In one embodiment, a zener diode is employed as the low voltage trigger apparatus (36), and in another embodiment low voltage trigger apparatus (36) is an n-channel MOSFET.

Thin film silicon on insulator semiconductor integrated circuit with

An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line V.sub.SS. The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).

Input/output electrostatic discharge protection circuit for an

A circuit and method for reducing a gate voltage of a transmission gate to prevent overvoltage that could damage or affect reliability of the transmission gate. The transmission gate resides in a charge pump circuit (41) coupled to a capacitor for generating a voltage greater than a power supply voltage. A buffer (44,45) receives a control signal and couples to a gate terminal of the transmission gate. The buffer (44,45) includes a power supply terminal that is coupled to a variable voltage reference (43). The variable voltage reference (43) provides a voltage that reduces the gate voltage of the transmission gate when an output voltage of the charge pump circuit reaches a predetermined voltage. The variable voltage reference (43) reduces a voltage range between logic levels provided by the buffer (44,45) to protect the transmission gate from an excessive voltage.

Circuit and method for reducing a gate volage of a transmission gate

A comparator (10) operates in comparator mode or in static leakage current test mode as determined by a control signal. In the comparator mode, the comparator receives a differential input signal for amplification through an analog differential front-end comparator input stage (31). The output of the comparator input stage is presented as a single-ended signal that is applied to an input of a buffer (32). The buffer amplifies the single-ended signal to digital logic levels. In test mode, the control signal enables a feedback circuit (36-42) from the output of the buffer back to its input and disables the differential front-end comparator input stage by removing the power supply. The last valid data state present at the output of the buffer is thus latched back to its input to allow static leakage current testing of down-stream circuitry without interference from the comparator drawing large static currents.

Comparator having latched output when disabled from the power supply

A transmitter/receiver circuit (19) for interfacing digital signals having logic levels of different voltage ranges. The transmitter/receiver circuit comprises a transmitter circuit (21) , a resistive load (23) , and a receiver circuit (22). The transmitter circuit (21) having a first input (24) which receives a digital signal of a first voltage range, a second input (26) which receives a control signal, a first terminal (27) and a second terminal (28). The resistive load (23) couples the first (27) and second (28) outputs together. The transmitter circuit (21) generates complementary digital signals at the first terminal (27) and the second terminal (28) having logic levels of a second voltage range. The transmitter circuit (21) can be disabled by the control signal. The receiver circuit (22) has a first and a second input coupled to the first (27) and second (28) terminals respectively and has an output (29). The receiver circuit (22) senses a voltage difference between the first (27) and second (28) terminals and generates a digital signal of the first voltage range at the output (29).

Transmitter/receiver circuit and method therefor

A digital voltage level translator circuit for interfacing circuitry operating at different voltages is described. An inverting digital voltage level translator circuit (11) has an input (12) and an output (13). The input is coupled to a transmission gate (18), an inverter (17), and a gate of a n-channel enhancement MOSFET (22). Transmission gate (18) is enabled by the inverter (17) when the input (12) is at a zero logic level. An output of transmission gate (18) is coupled to a gate of a p-channel enhancement MOSFET (21) and an output of a pull-up circuit (19). A zero logic level at the input (12) enables MOSFET (21) through transmission gate (18) and disables MOSFET (22) generating a one logic level at output (12). A one logic level at the input (12) enables MOSFET (22) transitioning output (13) to a zero logic level. Output (13) to a control input of pull-up circuit (19) and a zero logic level enables pull-up circuit (19) disabling MOSFET (21).

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Phoenix, AZ, United States of America

John H Quigley