Waferscale Integration, Inc.

John H Pasternak

Boaz Eitan

Yoram Cedar

Alexander Shubat

Reza Kazerounian

Alex Shubat

Arye Ziklik

Chang Hee Hong

An internal supply generator includes a charge pump, at least one regulator and a pump controller. The charge pump generates a charge pump signal whose voltage is higher than an input supply voltage. Each regulator produces a generally stable internal supply from the charge pump signal. The pump controller activates the charge pump whenever the charge pump signal falls to within a predetermined voltage of the voltage level of one of the internal supplies.

Duty cycle based charge pump controller

A charge pump whose charge transfer switches are formed of charge transfer transistors and single pole, double throw (SPDT) switches each of which controls the gate of its corresponding transistor. Each SPDT switch has two throw contacts, one which is connected to the left diffusion of its corresponding charge transfer transistor and the other of which is connected to ground. Thus, the SPDT switch selectively connects the gate of the charge transfer transistor it controls between a diode connection (the first contact) and ground (the second contact). As a result, the charge transfer switches of the present invention are both fully on (when diode-connected) or fully off (when connected to ground).

Charge pump circuit for voltage boosting in integrated semiconductor

A unit for maintaining the value of information regarding the state of a device during battery power includes one local latch per bit of state to be maintained. The latch is powered by a switched power supply which switches between main and battery power supplies. The latch latches the value of the bit of state when the value of the bit of state is valid and the power of the device is significant and maintains the value otherwise, typically during battery operation.

Unit for maintaining information regarding the state of a device during

A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit. The high power unit also includes control transistors for disabling its amplifier and leaker during the standby mode.

Unit for stabilizing voltage on a capacitive node

An embodiment of this invention provides an integrated circuit (IC) having a configurable peripheral port which includes an input/output pin, a multiplexer coupled to the input/output pin, volatile configuration bits to control the multiplexer, and non-volatile configuration bits to control the multiplexer and override the volatile configuration bits. One embodiment of an IC also includes a peripheral port as above and functional units, such as programmable array logic (PAL) and erasable programmable read only memory (EPROM), coupled to the multiplexer. In another embodiment, a non-volatile configuration bit from a functional unit configures an input/output pin when the configuration bit is not needed by the functional unit.

Peripheral port with volatile and non-volatile configuration

A race-free arithmetic operation circuit is disclosed. The circuit comprises a register file array, an arithmetic logic unit (ALU), and apparatus for controlling the input and/or the output signal of the ALU. The apparatus for controlling can be two level-sensitive latches, located before and after the ALU, or one master-slave flip-flop, located either before or after the ALU.

Growing community of inventors

Campbell, CA, United States of America

John H Pasternak