Cisco Technology, Inc.

3Com Corporation

Brenson, Inc.

John H Hughes

David M Emmett

Rajiv Dattatraya Kane

Mark S Isfeld

Bruce W Mitchell

Greg Walter

James S Cho

Hema Kapadia

Alan Zimmerman

Chris M Thomson

Roger D Rothhaar

A rapid method and apparatus for remapping the type of service (TOS) and source address information from an incoming communications packet according to the desired Quality of Service (QoS) required for the communications flow into a switch or router are described. The input source address field of the packet header is used to access a lookup table of corresponding source autonomous system (AS) labels. The appropriate AS label is combined with the input TOS yielding an intra-switch TOS optimized for the QoS appropriate to the received flow. Alternatively, the netID, a subset of the source address, may be used directly without resort to a lookup table. As a further alternative, the destination address may be used in conjunction with the above. The resulting intra-switch TOS expedites packet management and throughput in the switch/router, facilitating the efficient delivery of the required Quality of Service for that flow.

Hardware TOS remapping based on source autonomous system identifier

The present invention defines a system and method of routing packets using a hardware-based route cache with prefix length. When a router receives a packet, the router first searches for the routing information in the hardware-based route cache and if a match is found, the packet is forwarded to according to the routing information. The hardware-based route cache can be configured according to a search scheme employed by the router. The hardware-based route cache can be configured to provide network address length information for the destination addresses included in an incoming packet.

Hardware-based route cache using prefix length

The present invention describes a system and method of improving packet forwarding throughput in a router by reducing head of line blocking. In one embodiment of the present invention, incoming packets are stored in a packet reorder buffer. The packets are reordered for forwarding while maintaining the order of packets in a distinct flow. Packets belonging to a distinct flow require to be forwarded in the order that the router receives them. Packets from different flows are reordered such that their forwarding order can be different than the order in which they were received. Packets from the same flow are sent out in the same order as the router receives them.

Packet forwarding throughput with partial packet ordering

The present invention provides a mechanism whereby caching operations, such as prefetch and copyback operations, can be initiated by an external direct memory access (DMA) controller. This allows the DMA controller to govern the inclusion as well as exclusion of data from a processor cache in such as way as to avoid unnecessary cache faults, and to thereby improve system performance. Thus, the present invention effectively provides a synchronization mechanism between an external DMA controller and a processor cache.

DMA driven processor cache

The invention provides a method and system for rapid access to one or more M-tries for responding to header information. The M-tries are stored in a plurality of memory banks, which are accessed in parallel to provide relatively greater access throughput. Parts of the M-tries that are (or are expected to be) frequently referenced are stored in multiple banks of the memory, to provide concurrent simultaneous access for those parts of the M-tries for parallel lookup of multiple routes. Regions of the multiple banks of the memory can be dynamically reallocated to provide improved access through-put to those multiple banks. The invention can be applied to routing decisions in response to destination addresses, to combinations of destination and source addresses (either for unicast or multicast routing), to access control decisions, to quality of service decisions, to accounting, and to other administrative processing in response to header information.

Routing table lookup implemented using M-trie having nodes duplicated in multiple memory banks

An internetwork device manages the flow of packets of I/O data among a plurality of network interface devices. The internetwork device includes an I/O bus which is coupled to the plurality of network interface devices and a shared memory, for storing packets of I/O data and control structures needed by the plurality internetwork interface devices. The shared memory is also coupled to a processor bus, which connects to a processor and a processor memory. The processor memory is isolated from the shared memory, and is used for storing routines and internetworking information involved in routing packets of I/O data among the plurality of network interface devices. In this way, accesses between the processor and the processor memory are decoupled from accesses between the plurality of network interface devices. System performance is improved by storing copies of items from the shared memory in a processor cache located near the processor. Consistency rules are enforced between items in the shared memory and copies of the items in the processor cache through communications across the processor bus. Communications across the processor bus to enforce consistency rules are minimized by maintaining a shadow tag store near the shared memory, which keeps track of the items from the shared memory which are copied in the processor cache. Communications to enforce consistency rules only take place if the shadow tag store indicates that the processor cache contains an item of data from the shared memory which has been read from or written to.

High performance shared memory for a bridge router supporting cache

A bus protocol technique removes the transaction used for posting indications of events to the host processor from the bus. The invention takes advantage of the fact that addresses typically on a high speed bus contain fewer bits than the entire bus width. Particularly, for a 32 bit bus, the 32 bit address space is not always necessary. The remaining bits on the bus are used for an encoded event tag. A bus transaction involves a first bus transfer which provides an address for writing or reading data, along with the event tag. The event tag is detected and decoded by the destination, and the event is posted to the processor which monitors and responds to events, in a manner which is synchronous with completion of the transaction. Thus, after the transaction on the bus, the message subject of the transaction is waiting in the memory, and notification of the event has occurred automatically and synchronously with completion of the transfer.

Synchronous event posting by a high throughput bus

A router includes synchronous dynamic random access memory (SDRAM) based shared memory, with a controller configured to control the order in which the SDRAM access is granted to a plurality of interfaced components. In one embodiment, the controller's configuration minimizes the amount of time data from a particular source must wait to be read to and written from the SDRAM, and thus minimizes latency. In a different embodiment, the controller's configuration maximizes the amount of data read to and written from said SDRAM in a given amount of time and thus maximizes bandwidth. In yet another embodiment, characteristics of the latency minimization embodiment and the bandwidth maximization embodiment are combined to create a hybrid configuration.

Data processing system having memory controller for supplying current

A system for registering the primary colored images formed by a full color electrostatic plotter to create a high resolution composite color image. The print heads in the system include an active region of styli for forming image lines and left and right slack regions of styli. The active region may be shifted from side and increased in size to assure lateral registration. Longitudinal registration is achieved by adjusting the time interval between printing lines of successive primary images. Specific embodiments utilize line enhancement algorithms to ensure minimize line thickness in the image and to avoid the creation of artifacts in complex regions of the image and CCDs as sensors.

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San Jose, CA, United States of America

John H Hughes