Intel Corporation

John H Crawford

Edward Thomas Grochowski

Sailesh Kottapalli

Nhon Toai Quach

Chakravarthy Kosaraju

Brian S Morris

Suneeta Sah

Bharat Bhushan

Greg Mathews

Vinod Sharma

Kushagra V Vaid

Sreenivas Mandava

Douglas M Carmean

Paul S Ries

Paul S Diefenbaugh

Raj K Ramanujan

Gary N Hammond

Devadatta V Bodas

Donald B Alpert

Anil K Kumar

Roy M Stevens

Venkatesh Nagapudi

Mathew W Stefaniw

Ted Rossin

Kuljit Singh Bains

Alan G Gara

Shubhendu Sekhar Mukherjee

Carole Dulong

Eugene Gorbatov

Achmed Rumi Zahir

Tsvika Kurts

George Zacharias Chrysos

Gregory Scott Mathews

Allen Jay Baum

Richard J Greco

Justin J Song

Gautam B Doshi

Sundaravarathan R Iyengar

James Nadir

Moty Mehalel

Mustafiz R Choudhury

Stuart E Sailer

John Wai Cheong Fu

Ugonna C Echeruo

Carl C Scafidi

Ashish B Dixit

Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

Techniques for probabilistic dynamic random access memory row repair

A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.

Mapping a physical address differently to different memory devices in a group

Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

Refresh parameter-dependent memory refresh management

A method and system for managing power consumption and performance of computing systems are described herein. The method includes monitoring an overall power consumption of the computing systems to determine whether the overall power consumption is above or below an overall power consumption limit, and monitoring a performance of each computing system to determine whether the performance is within a performance tolerance. The method further includes adjusting the power consumption limits for the computing systems or the performances of the computing systems such that the overall power consumption is below the overall power consumption limit and the performance of each computing system is within the performance tolerance.

Managing power consumption and performance of computing systems

Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Techniques for determining victim row addresses in a volatile memory

An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset.

PCIE device power state control

A method and system for managing the operation of a computing system are described herein. The method includes determining a number of workloads on the computing system. The method also includes determining a number of performance-power states for each workload and a corresponding performance range and power consumption range for each performance-power state. The method further includes managing performance and power consumption of the computing system based on the performance-power states.

Managing the operation of a computing device by determining performance-power states

In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Synchronizing multiple threads efficiently

Memory refresh management

Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window.

Periodic activity alignment

An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the residency of activity patterns for efficient core hop scenarios is predicted to be large enough, a core is determined to be efficient and allowed. However, if efficient activity patterns are not predicted to be resident for long enough&#x2014;inefficient patterns are instead predicted to be resident for longer&#x2014;then a core hop request is denied. As a result, designers may implement a policy for avoiding core hops that weighs the potential gain of the core hop, such as alleviation of a core hop condition, against a penalty for performing the core hop, such as a temporal penalty for the core hop. Separately, idle durations associated with hardware power states for cores may be predicted in hardware. Furthermore, accuracy of the idle duration prediction is determined. Upon receipt of a request for a core to enter a power state, a power management unit may select either the hardware predicted power state, if the accuracy is high enough, or utilize the requested power state, if the accuracy of the hardware prediction is not high enough.

Mechanisms to avoid inefficient core hopping and provide hardware assisted low-power state selection

A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.

Method and apparatus for communication between two or more processing elements

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Saratoga, CA, United States of America

John H Crawford