Texas Instruments Corporation

Other

John H Carpenter, Jr

Joseph A Devore

Umar Jameer Lyles

Ross Eliot Teggatz

Karthik Kadirvel

Timothy Patrick Pauletti

Benjamin Lee Amey

Brett Jason Thompsen

David John Baldwin

Wayne Tien-Feng Chen

Tohru Tanaka

Amer H Atrash

Kenneth James Maggio

James Allen Kohout

Vijayalakshmi Devarajan

Toru Tanaka

Reed Wilburn Adams

Brian Lum-Shue-Chan

Vinod Mukundagiri

Zhihong You

J Randall Cooper

Andrew D Mitchell

Karthik Kadirevel

Karthik Kadirel

Systems and methods for cell anomaly detection are provided. The disclosed systems and methods of cell anomaly detection may use a single circuit to detect both cell-open and imbalance conditions. Disclosed embodiments may incorporate a continuous or a sampled time system (i.e. cell anomaly detection is performed when an enable signal is active). An example embodiment includes receiving voltages of a plurality of cells of a battery pack; converting the received voltages to currents; determining a maximum current of the currents; determining whether at least one of the currents is anomalous; and reporting the at least one anomalous current as indicative of a bad cell.

Systems and methods of battery cell anomaly detection

One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an input voltage. The power switch device includes a control terminal and a bulk connection. The system also includes a reverse voltage control circuit configured to passively couple the input voltage to one of the control terminal and the bulk connection in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative. The system further includes an output shutoff circuit configured to passively couple the output voltage to a neutral-voltage rail during the reverse voltage condition.

Reverse voltage condition protection in a power supply system

With batteries or cells, particularly lithium ion cells, it is important to determine when one or more cells have entered a fault condition (i.e., overvoltage or undervoltage). Conventional circuits employ measuring circuits that use multiple bandgap circuits and high voltage components. These conventional circuits, however, consume a great deal of area because of the use of these multiple bandgap circuits and the high voltage components. Here, a circuit is provided that reduces the number of bandgap circuits and reduces the number of high voltage components, reducing the area consumed and reducing the overall cost of production compared to conventional circuits.

Current based overvoltage and undervoltage detector

Systems and methods for determining a state of charge (SOC) of an electrical energy storage device are disclosed. In one embodiment, a system is provided for determining the SOC of an electrical energy storage device comprises at least one memristor coupled in series with the electrical energy storage device to monitor charge current and discharge current of the electrical energy storage device. The system also includes a readout controller configured to determine the SOC of the electrical energy storage device based on the resistance of the memristor.

Electrical energy storage systems and methods

Various apparatuses and methods for detecting cell connection status of a multi-cell battery are disclosed herein. For example, some embodiments provide an apparatus for detecting cell connection status of a multi-cell battery. The apparatus includes a battery cell input for each cell, a cell connection status detector for each cell, and at least one comparator. Each of the cell connection status detectors is connected to a battery cell input and has a current-based status indicator output. The at least one comparator is connected to the current-based status indicator outputs. Each of the plurality of cell connection status detectors floats in a different supply voltage range. The at least one comparator is referenced to a lower voltage potential than at least one of the plurality of cell connection status detectors.

Multi-cell power system controller

Methods and apparatus to detect voltage conditions of power supplies are disclosed. An example power supply monitor to detect fault conditions in a power supply includes a capacitive element communicatively coupled to the power supply, the capacitive element being configured to change state between a collapsed state and an open state in response to the power supply having a first voltage associated with a first fault condition of the power supply; a detector communicatively coupled to the capacitive element to detect a voltage spike generated from the state change of the capacitive element; and a signal generator to generate a fault signal in response to the voltage spike to indicate the power supply being in the first fault condition.

Methods and apparatus to detect voltage conditions of power supplies

A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage level, a reference oscillator that provides a reference clock signal and a plurality of voltage clamps that receive the plurality of different output voltage levels and output the plurality of different voltage level clock signals at respective output nodes. The plurality of voltage clamps are configured to clamp each of a given output node to a respective high-side voltage level in response to pulling up of the given output node toward a respective high output voltage level and to clamp each of the given output node to a respective low-side voltage level in response to pulling down of the output node toward a low output voltage level.

Apparatus for generating a plurality of different voltage level clock signals

Systems and methods for overvoltage and undervoltage detection may be implemented with a fully differential circuit that includes a coarse comparator and a band gap based fine comparator. The coarse comparator may determine if the battery is closer to an OV condition or an UV condition. Based on the output of the coarse comparator, the trip point of the fine comparator is adjusted. The outputs of both comparators are pull-up circuits whose output is decoded to determine if an OV or a UV condition has occurred. The systems and methods accomplish valid circuit outputs even when the voltage across the battery reduces to zero volts. This may be achieved by using an active low signal for the UV condition and an active high signal for the OV condition. Thus, when the battery voltage goes to zero, the circuit evaluates to the correct output.

Systems and methods of overvoltage and undervoltage detection

An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also comprises a diffusion region that is shared by each of the first ESD structure and the second ESD structure, such that the shared diffusion region forms a portion of at least one semiconductor junction associated with each of the first ESD structure and the second ESD structure.

Integrated ESD protection device

A method and apparatus for a Regulator that automatically configures to work in either SMPS mode or linear mode are disclosed. In one embodiment, the method includes inputting a constant current source to a CBoot_pin for a first predetermined amount of time upon enabling an autodetect circuit by a Regulator control circuit. The CBoot voltage at the CBoot_pin is then determined to see if the CBBoot voltage at the CBoot_pin is above a predetermined CBoot voltage for a second predetermined amount of time. The Regulator is then switched to operate in SMPS mode if the CBoot voltage is substantially continuously above the predetermined CBoot voltage for a second predetermined amount of time. The SMPS is operated in linear mode if the CBoot voltage is substantially continuously below or equal to the predetermined CBoot voltage for a second predetermined amount of time.

Automatic configuration for linear mode of switching power supply

Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

Circuits, devices and methods for regulator minimum load control

A thermal shutdown circuit for protecting a main FET that conducts a load current ILOAD. A reference circuit provides a temperature current proportional to temperature. A thermal sensor circuit has a resistor and generates an output signal signaling thermal shutdown when the voltage generated across the resistor by the temperature current exceeds a predetermined value. A sense FET having a size smaller than the main FET conducts a sense current ISENSE proportionately smaller than ILOAD. A current mirror mirrors a scaled current proportional to ISENSE to be conducted through the resistor, the scaled current being scaled so as to cause the voltage generated across the resistor to exceed the predetermined value when ILOAD exceeds a predetermined value.

Thermal shutdown trip point modification during current limit

A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal of the CAN bus. This CAN driver also provides improved symmetry between its differential output signals, CANH and CANL, and provides protection for its low voltage devices from voltage transients occurring on its output lines. The common-mode signal is sensed and buffered, then during the dominant to recessive transition, the bus signals are shorted to the buffered common mode voltage. Specifically, additional switches or transistors are used to pull the differential output signals, CANH and CANL, to the common mode signal Vwhen the state of the CAN bus transitions from dominant to recessive. This improvement minimizes high frequency spikes in the common-mode signal and eliminates DC shifts during transitions of the state of the CAN bus. A driver system may include a plurality of CAN drivers are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.

Common mode stabilization circuit for differential bus networks

Systems, methods and circuits for sense circuit calibration. In one particular case, a system is provided that includes a sense circuit, a calibration circuit, and a sample and hold circuit. The sense circuit provides a sense current that is derived from either a reference current or a load current depending upon the operational state. The calibration circuit includes a calibration amplifier electrically coupled to the reference current and to the sense current. The calibration amplifier outputs a calibration signal representing a difference between the reference current and the sense current. The sample and hold circuit is operable to store a value representative of the calibration signal, and useful in forming a calibration offset current applied to the sense current.

Systems and methods for sense FET calibration

A high voltage integrated circuit operable in a system having a low voltage reference, a high voltage reference, and a ground, for providing an output voltage higher than the high voltage reference. The integrated circuit includes a high voltage ground reference circuit, operable to provide a high voltage ground reference node. Also included is an oscillator, operable to provide a clock signal, the oscillator being connected to the high voltage reference and to the high voltage ground reference node. An isolated charge pump circuit is provided, operable to generate the output voltage and isolated in the integrated circuit from other circuitry.

Growing community of inventors

Rowlett, TX, United States of America

John H Carpenter, Jr