Motorola Corporation

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Freescale Semiconductors Inc.

John H Arends

William C Moyer

Jeffrey William Scott

Lea Hwang Lee

Charles W Kirtland

Steven L Schwartz

Keith E Diefendorff

John J Vaglica

Brian Christopher Kahne

Richard G Collins

James C Holt

James S Thomas

Christopher E White

An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.

Detecting byte ordering type errors in software code

Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.

Bus arbitration in low power system

A data processing system having multiple register contexts is described. One embodiment of the present invention uses a user programmable context control register for each of the multiple register contexts to allow for the mapping of portions of an alternate register context into a current register context. The context control register may also be used to provide for the sharing of common stack pointers among multiple register contexts. Therefore, when operating in a current register context, the context control register may be used to access portions of an alternate register context in place of accessing corresponding portions of the current register context.

Data processing system having multiple register contexts and method therefor

A processor () to coprocessor () interface supporting multiple coprocessors () utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor () and coprocessor () on a bi-directional shared bus () either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus () is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Method and apparatus for interfacing a processor to a coprocessor

A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is coupled to the storage device for providing data to the storage device and storing the data in the storage device. Interrupt control circuitry is coupled to the data execution circuitry, wherein the interrupt control circuitry interrupts the data execution circuitry. The data stored in the storage device is completely outputted, thereby having an associated interrupt latency resulting from the output of the stored data. The storage capacity of the storage device is changed dynamically to minimize the interrupt latency. The storage device has a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.

Method and apparatus for reducing interrupt latency by dynamic buffer sizing

Embodiments of the present invention relate generally to data processing systems having redirecting circuitry. For example, one embodiment relates to redirecting program flow in a data processing system having a data processor for executing instructions, and circuitry that redirects program flow by identifying an address corresponding to an instruction provided to the data processor for which program execution should be redirected when the instruction is decoded by the data processor. The circuitry also generates a control field having an offset corresponding to the address and using the control field to determine when program flow should be redirected. The circuitry creates a redirected address value by combining a portion of the control field with a predetermined address. The data processor implements redirection of program flow by utilizing the redirected address value. Embodiments also relate to redirecting data accesses and to redirecting program flow while remaining in a same execution context.

Data processing system having redirecting circuitry and method therefor

Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor ( ) to execute instructions and to fetch instructions from a memory ( ) according to a fetch size. This data processor ( ) comprises a first input ( ) to receive instructions, control logic ( ) to decode the instructions, and an instruction pipeline ( ) coupled to the first input ( ) and the control logic ( ). The instruction pipeline ( ) is responsive to a first signal ( ) to set the fetch size to one of a first size and a second size. The data processor ( ) therefore allows an instruction fetch policy to be altered based on the characteristics of an accessed device in order to achieve improved performance.

Method and apparatus for instruction fetching

A method for debug control in a pipelined data processor where an offset is determined for the program counter (PC) based on the state of the pipeline. The offset is subtracted from the PC value at the end of a debug session. The resultant PC value restarts fetching of a last unsuccessfully completed instruction. If the offset indicates a change to the PC value, the instruction register is adjusted to a nop to allow the pipeline to restart execution after the last successfully completed instruction. In one embodiment, the state of the machine is preserved prior to exception handling.

Debug controller in a data processor and method therefor

A processor ( ) to coprocessor ( ) interface supporting multiple coprocessors ( ) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor ( ) and coprocessor ( ) on a bi-directional shared bus ( ) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus ( ) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.

Data processor system having branch control and method thereof

A processor (,) to coprocessor (,) interface supporting multiple coprocessors (,) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (,) and coprocessor (,) on a bi-directional shared bus (,) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (,) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for providing operand feed forward support in a data processing system (10). In one embodiment, a scan chain (100) may be combined with a feed forward source Y (FFY) bit (64) to allow a user to update registers (50) and memory (18) during emulation and debug. In one embodiment, feed forward control circuitry (60) forces the content of the WBBR register (70) to be used as the Y source operand value for the first instruction to be executed following an update of scan chain (100). This allows debug module (14) to update processor registers (50) and/or memory (18) by initializing the WBBR register (70) with the desired value, asserting the FFY bit (64), and executing a processor (12) move instruction to the desired register in registers (50).

Method and apparatus for providing operand feed forward support in a

A processor to coprocessor interface supporting multiple coprocessors utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor and coprocessor on a bidirectional shared bus either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Method and apparatus for interfacing a processor to a coprocessor for

A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Growing community of inventors

Austin, TX, United States of America

John H Arends