Advanced Micro Devices Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Applied Micro Circuits Corporation

Compaq Computer Corporation, Inc.

Nexgen Microsystems

Redback Networks Inc.

Ampere Computing LLC

Nexgen, Inc.

Other

Ericsson Ab

Sun Microsystems Technology Ltd.

Telefonaktiebolaget Lm Ericsson (Publ)

Macom Connectivity Solutions, LLC

Advanced Micro Device, Inc.

John Gregory Favor

Joseph Byron Rowlands

Korbin S Van Dyke

David R Stiles

Richard Win Thaik

Matthew Ashcraft

Amos Ben-Meir

Seungyoon Peter Song

Christopher Patrick Nelson

Frederick Daniel Weber

Leonard Eric Shar

John S Thayer

Robert Alan Cargnoni

Dale Robert Greenley

Graham Ricketson Murphy

Paul G Chan

Harold L McFarland

Shrenik M Mehta

Peter N Glaskowsky

Laurent Rene Moll

Yu Qing Cheng

David Alan Kruckemyer

Edmund G Chen

Carlos Puchol

Jeffrey E Trull

Warren G Stapleton

Ivan Pavle Radivojevic

Gary W Thome

Stephan G Meier

Ruchi Wadhawan

Stephan Jourdan

Chris Lee Nelson

Kjeld Svendsen

Brian E Longhenry

Jonathan Christopher Perry

Daniel Fung

Bret Leslie Toll

Gregory G Minshall

Puneet Sharma

Mark E Roberts

George Van Horn Leming, Iii

Donald Alpert

John Christian Holst

Dennis L Wendell

Robert G Hathaway

Donald A Draper

Alfred Yeung

Luca Ravezzi

Walstein Bennett Smith, Iii

Eric Trehus

David S Oliver

Evan Gewirtz

Sean Philip Mirkes

Jorel D Hartman

Ravi Krishna

Benjamin S Wong

Imtiaz P Shaik

Joe Rowlands

Matthew W Ashcraft

Aspects disclosed in the detailed description include multi-level instruction scheduling in a processor. Related methods and systems are also disclosed. In one exemplary aspect, an apparatus is provided that comprises a scheduler circuit comprising a scheduling group circuit, a first selection circuit, and a second selection circuit. The scheduling group circuit comprising a plurality of groups of scheduling entries, each scheduling entry among the groups of scheduling entries each comprising an instruction portion and a ready portion, each group configured to have its scheduling entries written in-order. The scheduling group circuit is further configured to maintain group age information associated with each group of the plurality of groups. The first selection circuit is configured to select a first in-order ready entry from each group. The second selection circuit is configured to select the first in-order ready entry belonging to the oldest group based on the group age information for scheduling.

Apparatus, system, and method for multi-level instruction scheduling in a microprocessor

A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.

Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer

Various aspects provide for managing data associated with a cache memory. For example, a system can include a cache memory and a memory controller. The cache memory stores data. The memory controller maintains a history profile for the data stored in the cache memory. In an implementation, the memory controller includes a filter component, a tagging component and a data management component. The filter component determines whether the data is previously stored in the cache memory based on a filter associated with a probabilistic data structure. The tagging component tags the data as recurrent data in response to a determination by the filter component that the data is previously stored in the cache memory. The data management component retains the data in the cache memory in response to the tagging of the data as the recurrent data.

Data management for cache memory

Various aspects provide for mitigating voltage droop associated with a microprocessor (e.g., by controlling a clock associated with the microprocessor). For example, a system can include a microprocessor and a controller. The microprocessor can receive a clock provided by a clock buffer. The controller can control frequency of the clock provided by the clock buffer based on a voltage associated with the microprocessor. In an aspect, the controller can reduce the frequency of the clock in response to a determination that the voltage satisfies a defined criterion. Additionally, the controller can incrementally increase the frequency of the clock in response to another determination that the voltage satisfies another defined criterion after satisfying the defined criterion.

Clock control based on voltage associated with a microprocessor

Data managment for cache memory

A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.

Multi-level store merging in a cache and memory hierarchy

Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system

Method and apparatus for performing table lookup are disclosed. In one embodiment, the method includes providing a lookup table, where the lookup table includes a plurality of translation modes and each translation mode includes a corresponding translation table tree supporting a plurality of page sizes. The method further includes receiving a search request from a requester, determining a translation table tree for conducting the search request, determining a lookup sequence based on the translation table tree, generating a search output using the lookup sequence, and transmitting the search output to the requester. The plurality of translation modes includes a first set of page sizes for 32-bit operating system software and a second set of page sizes for 64-bit operating system software. The plurality of page sizes includes non-global pages, global pages, and both non-global and global pages.

Method and apparatus for performing table lookup

A load scheduler capable of limited issuing of out of order load instruction is disclosed. The load scheduler uses a max skipping threshold which limits the number of skipping load instructions and a max skipped threshold which limits the number of skipped load instructions. An address tag for a skipping instruction is stored in a skipping load instruction tracking unit when a skipping load instruction is issued. When a skipped load instruction issues, the address tag of the skipped load instruction is compared to the address tag of the skipping instruction to determine if a hazard from the out of order issuing of the skipping load instruction caused a hazard and must be flushed.

Threshold controlled limited out of order load execution

A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.

Outstanding load miss buffer with shared entries

A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. When missed load instructions are reissued from the outstanding load miss buffer, data for the missed load instructions are read from the load miss result buffer rather than the level one cache. Because the data is stored in the load miss result buffer, other instructions that may change the data in level one cache do not cause data hazards with the missed load instructions.

Load store unit with load miss result buffer

A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.

Load miss result buffer with shared data lines

A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

Digital processor for processing long and short pointers and converting each between a common format

A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.

Virtual core management

Growing community of inventors

Scotts Valley, CA, United States of America

John Gregory Favor