Aurora Systems, Inc.

Microunity Systems Engineering, Inc.

Telairity Semiconductor, Inc.

Fairchild Semiconductor Corporation

Fairchild Camera and Instrument Corp.

Jasper Display Corporation

John Gray Campbell

Edwin Lyle Hudson

Ban Pak Wong

Ronald L Cline

Luigi DiGregorio

Kim R Stevens

William Spencer Worley, Iii

Craig C Hansen

Timothy B Robinson

W Spencer Worley, Iii

Raymond Pinkham

Warren Robert Ong

W Spencer Iii Worley

A display system which includes a display controller, a display unit, and a light source is disclosed. The display controller includes a processor unit, a memory device, a voltage source and, optionally, a light source control unit. The display unit includes an array of pixel cells and circuitry to receive logic and control voltages and data and operate the display, a transparent counter electrode, and a liquid crystal layer disposed between the two alignment layers. The pixel cell includes a storage element, a DC balance control switch, a pixel voltage override circuit, an inverter able to select between two voltages available to it, and a pixel electrode/mirror. In different modes of operation the pixel mirror voltage may be determined by the storage element or by the pixel voltage override circuit. The display system may display images in one period and reset to a fixed state in another period.

Pixel circuit and display system comprising same

Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage Vand a low power supply voltage V. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

Power grid layout techniques on integrated circuits

Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage Vand a low power supply voltage V. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

A row decoder () for a video display system () wherein row output lines () of a row predecoder () are physically arranged such that adjacent iterations of the output lines () will generally not be switching simultaneously where addressing of the output lines () is sequential according to numbering and application. A ground trace () is provided between iterations of the output lines () which will be switching simultaneously. The output lines () provide input to a decoding circuit () within the row decoder (). A plurality iterations of predecoder subcircuits () each having a compliment of the output lines () is to provided such that all of the rows of a pixel array () can be addressed.

Row and/or column decoder optimization method and apparatus

A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

System and method for reducing peak current and bandwidth requirements in a display driver circuit

A row decoder (,) for a video display system (,) wherein row output lines (,) of a row predecoder (,) are physically arranged such that adjacent iterations of the output lines (,) will generally not be switching simultaneously where addressing of the output lines (,) is sequential according to numbering and application. A ground trace (,) is provided between iterations of the output lines (,) which will be switching simultaneously. The output lines (,) provide input to a decoding circuit (,) within the row decoder (,). A plurality iterations of predecoder subcircuits (,) each having a compliment of the output lines (,) is to provided such that all of the rows of a pixel array (,) can be addressed.

A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals. In various embodiments, the row sequencer, the sub-row sequencer, and/or the data path sequencer is/are responsive to data load instructions from a system, such that no Array Write commands are required to write data to a display.

Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit

A display includes a pair of global voltage supply terminals, for providing predetermined voltages, and a plurality of pixel cells. Each pixel cell includes a pixel electrode, a storage element for storing a data bit, and a multiplexer for selectively coupling the pixel electrode with one or the other of the global voltage supply terminals, depending on the value of the stored data bit. A voltage controller asserts predetermined voltages on the global voltage supply terminals, which are then transferred to the coupled pixel electrodes.

Display with multiplexed pixels for achieving modulation between

An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices coupled between the common output node and the base of the pull-down bipolar transistor. A second set of parallel MOS devices are coupled between the base of the pull-up output stage bipolar transistor and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Controlled slew rate output buffer

A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell includes two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal. A differential current signal representing the data stored in the memory cell is established in the complementary bit lines when the current source is selected and current is allowed to flow through one of the bipolar signal converters. The third and fourth ECL voltage potentials are chosen such that they ensure that the bipolar signal converters are not driven into saturation. In this way, read times are optimized. In addition, read times are reduced since peak-to-peak voltage of the current mode differential signal established across the complementary bit lines are reduced.

BiCMOS memory cell with current access

A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories are accessed depending on their proximity to the main I/O ports. Three parallel pipelines provide a data path to/from the main I/O ports and the sub-memories. The first pipeline functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

Accessing system that reduces access times due to transmission delays

A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent. The reference voltage source for the load current source is a modified band-gap regulator comprising a regulating transistor, a current source pair of transistors Q1 and Q2, and first, second, and third resistors. The third resistor changes the current relationships to provide the desired output voltage and temperature coefficient.

Gate having temperature-stabilized delay

A circuit technique for eliminating history-dependent skew and distortion of signals as they propagate through multiple gate stages in critical timing paths. It has been discovered that spurious effects can be attributed to signal coupling between stages, and that such coupling may be reduced by providing separate threshold voltage supplies for the critical gates. Each of the first and second gate stages comprises first and second transistors having their respective emitters coupled to a common circuit point, a current source coupled to the common circuit point to provide current flow through the transistors, with the relative current flow through said transistors being determined by the relative voltage levels at the respective bases. The output signal is taken from the collector of one of the transistors. First and second threshold voltage sources are coupled to the respective bases of the second transistors of the first and second gate stages. The threshold voltage sources are isolated from one another such that current drawn from either results in substantially no change in the voltage delivered by the other. This circuit technique has applicability to configurations where the first and second gate stages are cascaded and to configurations where the gate stages are parallel stages in different branches of the signal path.

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Los Altos, CA, United States of America

John Gray Campbell