Microsoft Technology Licensing, LLC

Other

John Grant Bennett

Trishul A Chilimbi

Karthik Kalyanaraman

Knut Magne Risvik

Michael Joseph Hopcroft

Vishesh Parikh

Jan O Pedersen

Chad P Walters

Chen Fu

Ketan K Dalal

Siamak Tavallaei

Raja Krishnaswamy

Shankar Pal

David Earl Heckerman

Christopher A Meek

Hui Shen

Robert Lovejoy Goodwin

Bo Thiesson

Monish Shantilal Shah

Marc Tremblay

Stefan Saroiu

David Robert Shutt

Lintao Zhang

Susan Elizabeth Carrie

Ahmad A Abdulkader

Dov Borovsky

Kamaljit S Bath

Weihu Wang

Jeffrey H Alger

Thulusalamatom Krishnamurthi Anand

Alan E Brandt

David A Marshall

Henry Allan Rowley

Bojie Li

Petr Slavik

Greg M Zaverucha

Ashwini S Khade

Peter A Tucker

Ravi Shankar Reddy Kolli

Bob Jenkins

Mike Hopcroft

Yue-Sheng Liu

Xiao-Song Yang

Greg Zaverucha

A compressed memory is divided into a plurality of segments, each segment is divided into a plurality of sub-segments, and each sub-segment in an uncompressed data space is compressed into block (s) in a compressed data space. Upon a read request to a sub-segment in a segment in compressed memory is received, the corresponding entry is firstly determined based on a first level address mapping between the sub-segment and the entry, and then the corresponding block (s) is determined based on a second level address mapping between the entry and the block (s). By use of two-level address mappings, the size of entry can be reduced, thereby achieving low metadata overhead. Moreover, the proposed data layout for compressed memory.

Hardware-based memory compression

Methods and computer storage media are provided for generating entries for documents in a forward index. A document and its document identification are received, in addition to static features that are query-independent. The document is parsed into tokens to form a token stream corresponding to the document. Relevant data used to calculate rankings of document is identified and a position of the data is determined. The entry is then generated from the document identification, the token stream of the document, the static features, and the positional information of the relevant data. The entry is stored in the forward index.

Efficient forward ranking in a search engine

Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.

Memory system with a predictable read latency from media with a long write latency

Systems and methods related to ensuring the integrity of data stored in a memory by using a watermark are described. An example method in a system including a processor and a memory may include receiving data for storage at an address in the memory. The method may further include after encoding the data with an error correction code to generate intermediate data having a first number of bits, reversibly altering the intermediate data with a watermark to generate watermarked data for storage in the memory, where the watermark is generated by applying a cryptographic function to a user key and the address, and where the watermarked data has a second number of bits equal to the first number of bits.

Ensuring the integrity of data stored in a memory by using a watermark

In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers. Based on a determination that the memory address range is to be assigned to the different specified performance tier, the memory address range may be assigned to the specified different performance tier.

Performance counters for computer memory

A memory device comprises a memory array, a counter unit, and a service unit. The memory array comprises cells arranged in rows and columns, wherein a subset of the cells in each of the rows holds a row activation count for each row. The counter unit, in response to an activation of the row caused by a read operation on at least a portion of the row, increments the row activation count for at least one of the rows prior to a completion of the read operation, and writes-back the row activation count in an incremented state to the subset of the cells in the row that held the row activation count prior to the activation. The service unit is coupled to the counter unit and performs a service with respect to one or more other rows, offset from the row, in response to the row activation count associated with the row satisfying service criteria.

Monitoring and mitigation of row disturbance in memory

A dynamic gain cell memory cell capable of storing multiple values is described herein. In one example, a memory cell may include an input, such as a first transistor. The memory cell may further include a capacitive element coupled to the input, where the capacitive element stores one or more values corresponding to one of multiple voltage levels. A sense transistor configured to operate in source-follower mode may be coupled to the capacitive element, where the charge on the capacitive element controls operation of the sense transistor, such as through a gate of the sense transistor. The memory cell may further include an output connected to the drain of the sense transistor, where current flows through the transistor when the output is activated to access the one or more values stored in capacitive element.

System for accurate multiple level gain cells

Systems and methods are described herein for electron-beam lithography. In some aspects, a photo electron emitter and channel array assembly (PEECAA) may include a photo-electron emitting cathode having a uniform planar surface and an array of beam channels proximate to the cathode. In some cases, at least one of the cathode or the array of beam channels is removable from the PEECAA. The array of beam channels may include a grid of apertures, a plurality of beam channels, and a shared lens array including a plurality of lenses proximate to an exit of the plurality of beam channels. Individual apertures of the grid of apertures align with individual beam channels to allow electrons from the cathode to pass through the array of beam channels and the shared lens array to form a pixelated pattern, such that, upon exposure to the target, the pixelated pattern is permanently formed on the target.

Modular parallel electron lithography

One or more pellicles protect a cathode, the pellicles comprised of a thin layer of material that allows electrons to pass while preventing contamination of the cathode from elements originating beyond the pellicle or contamination of an outside apparatus from elements originating on or near the cathode. The pellicle can be supported by an insulator, the insulator in turn supported by a deflecting layer. The pellicle can be maintained at a positive voltage relative to the cathode, such that a voltage gradient is created between the cathode and the pellicle that accelerates electrons emitted by the cathode away from the cathode. The pellicle is located at an appropriate distance from the cathode to allow electron transmission matching the energy of the electrons at that distance.

Low voltage electron transparent pellicle

In some examples, computer memory content movement may include ascertaining a request associated with content of computer memory. Based on a determination that the request is directed to the content that is to be moved from a source of the computer memory to a destination of the computer memory, a determination may be made as to whether the content is at the source, is in a process of being moved from the source to the destination, or has been moved from the source to the destination. Based on a determination that the content is at the source, the request may be performed using the source. Based on a determination that the content is in the process of being moved, the request may be performed using the source. Further, based on a determination that the content has been moved, the request may be performed using the destination.

Computer memory content movement

A data compression system includes a memory to store a plurality of predetermined prefixes corresponding to a plurality of classes of data. A classifying module is configured to receive data, receive a class of the data, and select a prefix to compress the data from the plurality of predetermined prefixes based on the data and the class of the data. A compressing module is configured to compress the data using the prefix. A header generating module is configured to generate a header including an indication of the prefix used to compress the data, and to output the header and the compressed data for storage or transmission. Using the prefix from the predetermined prefixes to compress the data eliminates an overhead of fetching the prefix from outside the data compression system.

Use of data prefixes to increase compression ratios

The described technology provides a system and method for sequential execution of one or more operation segments in an asynchronous event driven architecture. One or more operation segments may be associated and grouped into an activity of operation segments. The operation segments of an activity may be sequentially executed based on a queue structure of references to operation segments stored in a context memory associated with the activity. Any initiated operation segment may be placed on the queue structure upon completion of an associated I/O action.

Asynchronous sequential processing execution

A portion of the memory space, supported by memory chips that are being controlled by a memory controller logic, can be set aside and read requests directed to memory addresses within that portion can be redirected, by the memory controller logic, to other memory addresses at which is stored the data equivalent to the internal data of the memory controller logic that the memory controller logic seeks to return, thereby enabling the memory controller logic to indirectly return data to processes executing on the host computing device. Additionally, requests to write data to specific memory addresses, including memory addresses that can be within the set aside portion, can be interpreted, by the memory controller logic, as commands that the memory controller logic is to perform, and which impact its own internal data including commands to reset values, or start or end data collection, or other like commands.

Indirect data return from memory controller logic

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Sammamish, WA, United States of America

John Grant Bennett