Nvidia Corporation

Genesis Microchip Corporation

Vm Labs, Inc.

John George Mathieson

Louis A Cardillo

Eric R Smith

Shailender Chaudhry

David Nister

Sagheer Ahmad

Gary D Hicok

Mark Alan Overby

Karl Friedrich Greb

Sreenivas Reddy

Jonathan Sweedler

Ram Ganapathi

Ashok Srinivasan

Clement Farabet

Michael Truog

Mohammed Abdulla Yousuf

Michael Alan Ditty

Kevin Flory

Richard Miller

Mike Truog

Daniel Stewart Perrin

Sudhakaran Ram

Tai-Yuen Chan

Dan Hettena

Richard G Miller

David Lind Weigand

TY Chan

Daniel Perrin

Autonomous driving is one of the world's most challenging computational problems. Very large amounts of data from cameras, RADARs, LIDARs, and HD-Maps must be processed to generate commands to control the car safely and comfortably in real-time. This challenging task requires a dedicated supercomputer that is energy-efficient and low-power, complex high-performance software, and breakthroughs in deep learning AI algorithms. To meet this task, the present technology provides advanced systems and methods that facilitate autonomous driving functionality, including a platform for autonomous driving Levels 3, 4, and/or 5. In preferred embodiments, the technology provides an end-to-end platform with a flexible architecture, including an architecture for autonomous vehicles that leverages computer vision and known ADAS techniques, providing diversity and redundancy, and meeting functional safety standards. The technology provides for a faster, more reliable, safer, energy-efficient and space-efficient System-on-a-Chip, which may be integrated into a flexible, expandable platform that enables a wide-range of autonomous vehicles, including cars, taxis, trucks, and buses, as well as watercraft and aircraft.

Systems and methods for safe and reliable autonomous vehicles

Embodiments of the present technology provide for migrating processes executing one any one of a plurality of cores in a multi-core cluster to a core of a separate cluster without first having to transfer the processes to a predetermined core of the multi-core cluster. Similarly, the processes may be transferred from the core of the separate cluster to the given core of the multi-core cluster.

Processor cluster migration techniques

Memory access techniques, in accordance with embodiments of the present technology, redirect memory access requests received from a baseband processor to shared memory coupled to an application processor. The techniques enable substantially real time read and write accesses by the application and baseband processors to the shared memory coupled to the application processor.

Shared memory access techniques

According to an aspect of the present invention, the communication between processors and peripheral controllers is provided using packets. In an embodiment, the access requests are specified according to a common format such that all the information required for performing each access request is included in a single packet and sent to the peripheral controller. The peripheral controller performs the access request on the external device and generates a response. According to another aspect, the packet format enables the peripheral controller to send responses, requests originating from the external devices and interrupt requests. According to yet another aspect, the packets from processors are first stored in a random access memory (RAM) and a DMA controller retrieves the packets and delivered to the respective peripheral controllers.

Communication between a processor and a controller

A media processing system is provided including a DRAM that includes a plurality of storage locations for storing digital data being processed by said media processing system, said digital data including video data that is compressed in a standardized format, a system for processing said digital data that includes said standardized format compressed video data to produce compressed video images and image data, a system for decoding said standardized format compressed video images to generate full motion video pixel data, a system for sharing said DRAM between said processing means and said decoding means, and a system for producing a full motion video signal from said full motion video pixel data. The media processing system may also have a system for multiplying or combining a first pixel by a second pixel in a single clock cycle. The media processing system may have a plurality of processing elements connected together in parallel, a system for controlling said processing elements with instruction words that have a predetermined number of instructions, and a system for distributing data simultaneously to each of said processing elements.

Systems and methods for efficient processing of multimedia data

In accordance with the invention, a multi-processing unit system including a plurality of processing units in direct communication via a communication bus is presented. The system includes a communication bus arbiter having a communication packet multiplexer. Each of the processing units include a communication bus interface comprising a transmitter interface and a receiver interface. Each of the transmitter interfaces are connected to the communication packet multiplexer of the communication bus arbiter via separate 32-bit interfaces. Each of the receiver interfaces is connected to the communication packet multiplexer of the communication bus arbiter via a single 32-bit bus. The system may further comprise a first control signal connection means for communicating control signals between the transmitter interface and the communication bus arbiter and a second control signal connection means for communicating control signal between the receiver interface and the communication bus arbiter.

Communication bus for a multi-processor system

A system and method for compressing and decompressing variable length instructions contained in variable length instruction packets in a processor having a plurality of processing units is provided that has a compression system with a system for generating an instruction packet containing a plurality of instructions, a system for assigning a compressed instruction having a predetermined length to an instruction within the instruction packet, a shorter compressed instruction corresponding to a more frequently used instruction, and a system for generating an instruction packet containing compressed instructions for corresponding ones of said processing units. The decompression system has a system for storing a plurality of said instruction packets in a plurality of storage locations, a system for generating an address that points to a selected variable length instruction packet in the storage system, and a decompression system that decompresses said compressed instructions in said selected instruction packet to generate a variable length instruction for each of said processing units. The decompression system may also have a system for routing said variable length instructions from the decompression system to each of said processing units.

Instruction compression and decompression system and method for a

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Los Gatos, CA, United States of America

John George Mathieson