Agilent Technologies, Inc.

Hewlett-packard Company

Avago Technologies General IP (singapore) Pte. Ltd.

Other

John G Rohrbaugh

Jeffrey R Rearick

Shad R Shepston

Jeff Rearick

Michael J Bennett

Robert W Proulx

Thomas H Baker

Mercedes E Gil

Christopher M Juenemann

Daryl H Allred

Mercedes P Gil

A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), includes an IC logic element, a scan chain, and a calibration circuit including a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.

Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)

Hierarchically-controlled automatic test pattern generation (ATPG) is provided. One embodiment comprises a method for automatically generating test patterns for testing a device under test. Briefly described, one such method comprises the steps of: receiving a hierarchical model of a device under test, the hierarchical model comprising at least one low-level design component and at least one high-level design component which contains the low-level design component; selecting a fault to be detected in the device under test; and performing an automatic test pattern generation (ATPG) algorithm on the design components based on the hierarchy of the hierarchical model.

Hierarchically-controlled automatic test pattern generation

Methods for testing integrated circuits (ICs) are provided. An embodiment of a method comprises: electrically interconnecting automated test equipment (ATE) with the IC; providing at least one stimulus such that the IC determines the presence of a leakage current of the first pad; and receiving information corresponding to the leakage current of the first pad. Systems also are provided.

Systems and methods for facilitating testing of pads of integrated circuits

Integrated circuits (ICs) are provided. A representative IC includes a first pad electrically communicating with at least a portion of the IC. The first pad includes a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. The first receiver also is configured to provide, to a component internal to the IC, a first receiver digital output signal in response to the first pad input signal. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the driver tristate leakage current of the first pad. Methods, computer-readable media, systems and other ICs also are provided.

Systems and methods for facilitating testing of pad drivers of integrated circuits

A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

System and method for evaluating an integrated circuit design

A preferred integrated circuit for facilitating receiver trip level testing functionality includes a first pad which incorporates a first driver and a first receiver. The first driver is configured to provide a first pad output signal to a component external to the IC. The first receiver is configured to receive a first pad input signal from a component external to the IC, and to provide a first receiver digital output signal to a component internal to the IC in response to the first pad input signal. Additionally, a first test circuit is provided that is arranged internal to the IC, with the first test circuit being adapted to provide information corresponding to at least one receiver trip-level characteristic of the first receiver of the first pad. Systems, methods and computer readable media also are provided.

Systems and methods for facilitating testing of pad receivers of integrated circuits

A method and apparatus of carrying out a computer assisted analysis function on a hierarchical circuit model. The method is carried out by inputting the hierarchical circuit model, specifying at least one circuit block within the hierarchy as a target of the function on the target block, and simplifying the hierarchical circuit model by deleting circuit blocks not affecting the analysis function, to produce a simplified hierarchical circuit model. A computer assisted analysis function can then be carried out on the simplified hierarchical circuit model. The model is simplified by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block is a circuit block desired in the computer assisted analysis and if so keeping the circuit block as part of the simplified hierarchical circuit model; and by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block comprises a parent circuit block containing a child circuit block desired in the computer assisted analysis and if so keeping the parent circuit block as part of the simplified hierarchical circuit model.

Partitioning integrated circuit hierarchy

The present invention is generally directed to an improved automatic test pattern generator for generating test patterns that are used by an integrated circuit testing device. In accordance with one aspect of the invention, a method is provided for generating a set of test vectors for testing an integrated circuit, each test vector of the set of test vectors containing a plurality of bits defining test inputs for the integrated circuit. The method includes the steps of defining a list of faults for the integrated circuit, and generating at least one test vector that defines values for those inputs necessary to detect at least one target fault selected from the list of faults, the values comprising only a portion of the bits of the at least one test vector, wherein a remainder of the bits in the at least one test vector are unspecified bit positions. The method further includes the step of setting the values of a plurality of the unspecified bit positions using a non-random filling methodology.

Apparatus and method for generating a set of test vectors using nonrandom filling

Methods for testing integrated circuits (ICs) are provided. An exemplary method, in which the IC has a first pad configured as a signal interface for components external to the IC, the first pad having a receiver configured to receive an input signal from a component external to the IC, comprises: electrically interconnecting automated test equipment (ATE) with the IC; providing at least one stimulus to the IC such that the IC measures a receiver termination characteristic of the first pad; and receiving information corresponding to the receiver termination characteristic of the first pad. Systems and integrated circuits also are provided.

Systems and methods for testing receiver terminations in integrated circuits

Integrated circuits (ICs) are provided. A representative IC includes a first pad that incorporates a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the driver strength of the first pad. Systems, methods, computer-readable media and other ICs also are provided.

Systems and methods for facilitating driver strength testing of integrated circuits

A preferred system for facilitating automated test equipment functionality within integrated circuits includes automated test equipment (ATE) configured to electrically interconnect with an integrated circuit and to provide at least one signal to the integrated circuit. A first parametric test circuit, internal to the integrated circuit, also is provided. The first parametric test circuit is adapted to electrically communicate with the automated test equipment so that, in response to receiving a signal from the automated test equipment, the first parametric test circuit measures at least one parameter of a first pad of the integrated circuit.

Systems and methods for facilitating automated test equipment functionality within integrated circuits

A preferred integrated circuit (IC) includes a first pad electrically communicating with at least a portion of the IC. The first pad includes a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. The first receiver also is configured to provide, to a component internal to the IC, a first receiver digital output signal in response to the first pad input signal. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the driver clock-to-q time of the first pad. Systems, methods and computer-readable media also are provided.

Systems and methods for testing integrated circuits are provided. One such method comprises: providing a target fault list corresponding to an integrated circuit, the target fault list including at least a first fault and a second fault; measuring a relationship between the first fault and the second fault, the relationship corresponding to which of the first fault and the second fault is more readily detected by automatic test pattern generation; ordering the first fault and the second fault within the target fault list in a manner corresponding to the relationship; and performing automatic test pattern generation based upon an order of the faults of the target fault list. Systems and other methods also are provided.

Systems and methods for testing integrated circuits

A preferred integrated circuit (IC) includes a first pad electrically communicating with at least a portion of the IC. The first pad includes a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. The first receiver also is configured to provide, to a component internal to the IC, a first receiver digital output signal in response to the first pad input signal. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the receiver setup time and/or the receiver hold time of the first pad. Systems and methods also are provided.

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Fort Collins, CO, United States of America

John G Rohrbaugh