Advanced Micro Devices Corporation

International Business Machines Corporation

John G Pellerin

James N Pan

Jon D Cheek

Mark W Michael

William George En

Derick J Wristers

Srikanteswara Dakshina-Murthy

Suzette Keefe Pangrle

Michael John Hargrove

George Jonathan Kluth

Darin A Chan

Douglas J Bonser

Richard J Carter

Wen-Jie Qi

Ernesto A Gallardo

Johannes F Groschopf

Ramkumar Subramanian

Michael Patrick Chudzik

Robert Louis Dawson

Lu You

Richard J Huang

Rajarao Jammy

Dawn M Hopper

Thomas Werner

Linda R Black

Mark Kelling

Hai Hong Wang

Christof Streck

Ramkumar Subramanion

Edward Asuka Nomura

A method of fabricating a semiconductor device having a transistor with a metal gate electrode and a gate dielectric layer includes forming a protective layer on the gate dielectric layer and forming a metal gate electrode over the protective layer. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Replacement metal gate transistors with reduced gate oxide leakage

A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.

Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the SC device, and is formed substantially from the same metal as is the LC metal gate.

Integrated circuit having long and short channel metal gate devices and method of manufacture

A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.

Integrated circuit long and short channel metal gate devices and method of manufacture

A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective gate dielectric thicknesses for the different gate dielectrics separating the channels, and different respective silicon channel thicknesses for the different channels.

Multi-operational mode transistor with multiple-channel device structure

A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Low-power multiple-channel fully depleted quantum well CMOSFETs

A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.

Method of forming a semiconductor arrangement with reduced field-to active step height

STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 &#x212b;. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.

Method of reducing STI divot formation during semiconductor device fabrication

A semiconductor device with a replacement metal gate and the process for making the same removes a dummy gate from a semiconductor device. Within the recess left by the dummy gate is a silicon layer on a gate dielectric layer. A replacement metal is deposited on the thin silicon layer and then reacted with the silicon layer to form a metal-rich silicon layer on the gate dielectric layer.

Replacement metal gate transistor with metal-rich silicon layer and method for making the same

A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.

Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

SOI device with different silicon thicknesses

The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.

Method to reduce parasitic capacitance of MOS transistors

The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.

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Austin, TX, United States of America

John G Pellerin