Xilinx, Inc.

John G O'Dwyer

Brendan Farley

Woon Wong

Paul Newson

John Edward Mcgrath

Schuyler E Shimanek

John E McGrath

Brian C Gaide

Patrick J Crotty

John K Jennings

Wayne Edward Wennekamp

Edward Cullen

Roger D Flateau, Jr

Sanford L Helton

Jinsong Oliver Huang

Mikhail A Wolf

Charles D Laverty

An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Programmable device having hardened circuits for predetermined digital signal processing functionality

Method and apparatus for sharing an analog signal for use by a plurality of devices are disclosed. In some implementations, the analog signal may be generated by a controller. The controller also may generate a control signal to determine when other devices use the analog signal. In one implementation, the control signal may be a token that may be transmitted and received by the other devices. If a device possess the token, then the device may use the analog signal. If the device does not possess the token, then the device may not use the analog signal. In another implementation, the controller may transmit a peer-to-peer message to a selected device. When the selected device receives the peer-to-peer message, then the selected device may use the analog signal. In this manner, the controller ensures that only one device at a time may use the analog signal.

Time-multiplexed distribution of analog signals

An apparatus for clock deskew includes: a first delay element configured to receive a clock signal from a clock, wherein the delay element comprises multiple delay lines; a first multiplexer coupled to the multiple delay lines; a sensor configured to sense a voltage, a temperature, or both, and to provide a sensor output based at least on the sensed voltage and/or the sensed temperature; and a converter configured to receive the sensor output, and to generate a converted signal; wherein the first multiplexer is configured to provide a delay line output from one of the multiple delay lines based at least in part on the converted signal.

Distributed voltage and temperature compensation for clock deskewing

A method and apparatus for aligning an input signal to a clock signal in an integrated circuit are disclosed. The method includes receiving an input signal; determining whether the input signal is arriving too early or too late via a plurality of delay lines; and adjusting a delay of the plurality of delay lines in accordance with a result of the determining.

Method and apparatus for dynamically aligning high-speed signals in an integrated circuit

A technique is provided that involves: configuring a clock generation circuit to output a first signal having a first frequency that is one of a plurality of frequencies that are different; generating in a clock section of a further circuit as a function of the first signal a second signal having a second frequency that is one of the plurality of frequencies other than the first frequency; and configuring the clock section to supply to the further circuit a clock signal that is one of the first and second signals.

Method and apparatus for distributing clock signals

A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.

Signal calibration for memory interface

A method and apparatus for dynamically aligning high-speed signals in an integrated circuit are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and at least one input/output interface coupled to the logic fabric. The input/output interface includes a plurality of input/output sites and an edge detector coupled to the plurality of input/output sites for detecting an edge in an input signal received by the integrated circuit. A plurality of delay lines are used to determine whether the input signal arrives too early or too late compared to a clock signal in the integrated circuit, and delays in the delay lines are adjusted to align the input signal with the clock signal in the integrated circuit.

In one embodiment, a method and apparatus for configuring the internal memory cells of an integrated circuit through the logic fabric are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and a plurality of input/output blocks coupled to the logic fabric, wherein the plurality of input/output blocks is positioned around the periphery of the logic fabric. The plurality of input/output blocks therefore forms a ring around the logic fabric, wherein a data path and a clock path are formed along the periphery of the logic fabric through the plurality of input/output blocks.

Method and apparatus for configuring the internal memory cells of an integrated circuit

In one embodiment, a method and apparatus for shifting the bits of a data word are disclosed. For example, a deserializer according to one embodiment includes an input register bank for capturing serial data comprising n bits, an intermediate register bank, and a strobe mux coupled to an input of the intermediate register bank. An input of the intermediate register bank is coupled to an output of the input register bank. The strobe mux comprises a single multiplexer configured to select a bitslip strobe signal that controls an order in which the n bits of the serial data are captured in the intermediate register bank.

Method and apparatus for shifting the bits of a wide data word

A programmable delay line includes a first oscillator that is enabled and generates a plurality of clock cycles of a clock signal in response to a transition of the input signal. A first programmable ripple counter is coupled to the first oscillator, counts with each successive clock cycle to a programmed count, and generates a first signal in response to reaching the programmed count. A control circuit is coupled to the first oscillator and to the first programmable ripple counter. The control circuit transitions the output signal and disables the first oscillator in response to the first signal.

Ripple counter based programmable delay line

Multiple supply voltage select circuit for use with reduced supply voltage levels and method for using same are described. A first and second set of P-channel transistors are used for voltage pull-up at a common node using two supply voltages, respectively. A P-channel transistor from each of the sets is gated by output of a respective level shifter. Both of the level shifters are biased with a higher of the two supply voltages. First and second inputs are respectively provided to the level shifters and to gates of other P-channel transistors of each of the sets.

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Maynooth, Ireland

John G O'Dwyer