Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Hewlett-packard Corporation

John G McBride

Jan Kok

Ted B Ziemkowski

Shen Lin

Ted Scott Rakel

Thomas N Indermaur

Osamn S Nakagawa

A method and apparatus for evaluating the design quality of an integrated circuit design. The design to be evaluated comprises a plurality of static gates, such as, for example, NAND and NOR gates. The apparatus of the present invention comprises a computer configured to execute a rules checker program. The rules checker program analyzes each of the static gates to determine whether or not the gates meet acceptable noise immunity requirements. In order to perform this task, the rules checker program constructs models of each gate. The models emphasize or de-emphasize the strengths of certain FETs of the gate in response to noise on inputs to the gate for different logic states of the inputs. For each model, the rules checker program obtains a PFET-to-NFET width ratio. These ratios are utilized to obtain noise levels from a lookup table. Noise levels on the inputs to the gate are derived, either by calculation or simulation. These derived noise levels are then compared with the noise levels obtained from the lookup table to determine whether or not the gate being evaluated meets acceptable noise immunity requirements.

Method and apparatus for evaluating the design quality of network nodes

A method and apparatus for evaluating an integrated circuit design to determine whether elements in the integrated circuit are feedback elements. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether or not an element being evaluated is a feedback element. The rules checker program preferably performs a first routine that determines whether an element being evaluated is a feedback element in a special type of circuit. If the first routine determines that it has not detected the special type of circuit, or special case, the rules checker program begins executing a second routine. If the first routine determines that it has detected a special case, the routine ends. The second routine performs several checks to determine whether or not an element being evaluated is a feedback element. The first and second routines are designed to ensure that the order of the checks maximize efficiency in the manner in which the rules checking task is performed, although the invention is not limited to the particular order.

Method and apparatus for determining whether an element in an integrated circuit is a feedback element

The present invention is generally directed to a system and method for performing evaluation tests on a circuit design. Specifically, the present invention is directed to a system and method that controllably executes test routines on a netlist file. Broadly, the system of the present invention is a software package that is configured to execute a wide variety of tests, checks, or evaluations on a circuit design, as defined by a netlist file. An inventive aspect lies in the controllable execution of the various tests, checks, and evaluations, whereby certain tests may be omitted. In accordance with this novel aspect of the invention, the program may look to one or more files that contain a listing of tests that would otherwise be performed by the program, but which the program omits if listed in any of the one or more exclusion files. Preferably, the system employs two such exclusion files: one which is located in a 'local' directory (i.e., the same location from which the program is being launched), and a 'global' exclusion file, which is located in a predetermined, or specified, location.

System and method for executing tests on an integrated circuit design

An electrical rules checker system and method are provided to identify tri-state logic from a netlist. In accordance with one aspect of the invention, a method identifies tri-state logic from a netlist by selecting a circuit configuration to be identified, and then identifying any of the circuit configurations at the node, and identifyng any probable circuit configurations at the node. In accordance with another aspect of the invention, a system is provided for identifying tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist.

Electrical rules checker system and method using tri-state logic for electrical rule checks

A method and apparatus for evaluating an integrated circuit design to determine whether a pass FET is part of a RAM cell structure in the integrated circuit design. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a pass FET in the integrated circuit is part of a RAM cell structure of the integrated circuit. The rules checker program of the present invention evaluates each pass FET which is channel-connected at one of its terminals to a latch node and determines whether that pass FET is channel-connected at one of its other terminals to the drain or source terminal of at least one other pass FET. If so, the pass FET being evaluated is part of a RAM cell structure. In accordance with the preferred embodiment of the present invention, the rules checker program evaluates nodes in an integrated circuit to detect latch nodes. When a latch node is detected, the rules checker program determines whether or not a single pass FET is connected by either its drain or source terminal to the latch node. If so, the rules checker program obtains the pointer to the other drain or source terminal of the pass FET. The rules checker program then obtains a list of elements that are channel-connected to the node designated by the pointer and searches the list to determine whether or not more than one pass FET is contained in the list. If so, the rules checker program determines that the pass FET connected to the latch node is part of a RAM cell structure as opposed to a latch structure.

The present invention provides a method and apparatus for determining the strongest and weakest paths from a supply of a gate comprised in an integrated circuit to an output node of the gate and from ground to the output node of the gate. The apparatus comprises a computer capable of being configured to execute a rules checker program. When the rules checker program is executed by the computer, it analyzes information relating to the network and determines the strongest and weakest paths from the supply to the output node of the gate and from ground to the output node of the gate. The rules checker program calculates the effective widths of the PFET and NFET networks in the gate being evaluated and uses this information to determine the strongest and weakest paths from the supply to the output node of the gate and from ground to the output node of the gate. Once the strongest and weakest paths have been determined, information relating to the strongest and weakest paths is utilized by the rules checker to model the gate as an inverter having a single PFET and a single NFET. Two models are generated for this purpose. One model corresponds to the strongest PFET and the weakest NFET and a second model corresponds to the strongest NFET and the weakest PFET. The PFET-to-NFET ratios of the models can be used to determine various design characteristics of the gate, such as, for example, the noise immunity of the gate.

Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit

The present invention provides a method and apparatus for evaluating nodes in an integrated circuit to determine whether or not networks containing the nodes meet certain design criteria. The method and apparatus of the present invention are embodied in a rules checking system which evaluates the nodes in the integrated circuit to determine whether or not the networks in the integrated circuit comply with the design rules. Compliance with any particular rule is verified by performing one or more checks on the particular node being evaluated. Some checks require less time to perform than others. In some cases, the result of a single check can provide a determination as to whether or not the network containing the node being evaluated complies with the rule associated with the particular check. Furthermore, some checks are less expensive in terms of the amount of time required to perform them than other checks. Therefore, it is desirable to prioritize the order in which the checks associated with a particular rule are performed so that the rules checking tasks are performed with maximum efficiency. The rules checking system of the present invention prioritizes the checks so that efficiency in the overall rules checking process is maximized.

Method and apparatus for prioritizing the order in which checks are performed on a node in an integrated circuit

A method and apparatus for evaluating an integrated circuit design to determine the effective wire resistance at a receiver node of a receiver gate disposed in a network in the integrated circuit. The rules checker apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to calculate the effective wire resistance at the receiver node. The rules checker of the present invention traverses a path from the output node of the driver gate to the receiver node of the receiver gate and recursively sums the values of the parasitic resistances encountered along the path to maintain a total resistance value. Once the rules checker determines that the receiver node has been reached, the rules checker determines that the total resistance value equals the effective wire resistance at the receiver node. The rules checker also is capable of determining whether or not a path being traversed is a false path, i.e., a path that does not lead to the receiver node. When the rules checker determines that a path being traversed does not lead to the receiver node, the total resistance value is set to 0 so that the parasitic resistances along a false path are not taken into account in calculating the effective wire resistance at the receiver node.

The present invention is generally directed to a system and method for identifying nodes in a circuit design that are susceptible to floating. In accordance with one aspect of the invention, a method identifies nodes susceptible to floating by first detecting a node that is an output of a pass gate. The method then evaluates the circuit structure surrounding the node to ensure that the surrounding circuit structure is not one of several permissible structures. In this regard, the method ensures that the node is not an output node of a static gate. It also determines that the node is not an output of a multiplexer. If further verifies that the node is not an output of a pass gate that is always on. In addition, the method determines that the node drives a FET gate. In accordance with another aspect a computer readable storage medium, containing program code for evaluating a netlist, may be provided to detect a node that is susceptible to floating comprising. In this regard, the computer readable medium includes a first code segment configured to detect a node that is an output of a pass gate. It further includes a second code segment configured to ensure that the node is not an output node of a static gate. In addition, the computer readable medium includes a third code segment configured to determine that the node is not an output of a multiplexer. It further includes a fourth code segment configured to verify that the node is not an output of a pass gate that is always on. Finally, the computer readable medium includes a fifth code segment configured to determine that the node drives a FET gate.

System and method for detecting nodes that are susceptible to floating

An Electrical Rules Check (ERC) methodology ensures the quality of an electrical circuit through the creation of up to four different data structures, corresponding to one or more nodes, one or more small nodes, one or more non-resistor elements, and one or more resistor elements of the circuit, that are used by an ERC program running on one or more processors. The creation of data structures for small nodes and resistor elements in which less information need be stored for use by the ERC program minimizes the amount of data storage that must be utilized.

Framework for rules checking utilizing resistor, nonresistor, node and small node data structures

The present invention provides a method and apparatus for determining the RC delays associated with branches of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. When the rules checker algorithm is executed, the algorithm analyzes information relating to the network and determines the total effective RC delays between the output of a driver gate of the network and the inputs of one or more receiver gates of the network. In accordance with the preferred embodiment of the present invention, the rules checker algorithm performs these tasks by: (1) analyzing each branch of the network to determine the primary RC delay of each branch assuming the branch being analyzed corresponds to the worst case RC delay of the network; (2) analyzing each branch of the network assuming one of the other branches of the network corresponds to the worst case RC delay of the network and determining the effect that the resistances and capacitances of the branch being analyzed would have on other branches; (3) determining the total effective RC delay of each branch by combining the primary RC delay of each branch with the effect that the other branches have on the branch being analyzed; and (4) determining which branch of the network has the largest total effective RC delay.

Method and apparatus for determining which branch of a network of an integrated circuit has the largest total effective RC delay

A method is disclosed for estimating inductive coupling noise of a signal on a transmission line in a circuit design stored in a computer memory. The method determines the capacitive coupling noise on the signal, adds inductive coupling noise, and compares the total to a specified maximum amount of noise. The inductive coupling is a percentage of a supply voltage, which percentage varies depending upon the transition rate of the signal, the resistance of the line, and the gate capacitance of a load on the line. The inductive coupling varies based on the circuit design and may be stored in a table having inductive coupling values for multiple design conditions. The table is created using a field solver to determine line characteristics and a circuit simulator to simulate inductive coupling noise. For each set of initial conditions, a worst-case inductive coupling value is recorded in the table.

Method and system for screening a VLSI design for inductive coupling noise

An electrical rules checker system and method are provided to report any errors discovered during appraisal of an element at a node in a netlist. In accordance with one aspect of the invention, a method selects a circuit configuration to be identified. Next, identify any element at a node, equal to or virtually equal to said circuit configuration. Then, the element equal to and virtually equal to said circuit configuration is appraised. Finally, any error discovered during appraisal of the element at the node is reported. hi accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by a code segment selecting a circuit configuration to be identified. A second code segment identifies any element at a node, equal to said circuit configuration, and a third code segment identifies any element at the node virtually equal to said circuit configuration. A fourth code segment appraises the element equal to and virtually equal to the circuit configuration, and a fifth code segment reports any error discovered during appraisal of the element at the node.

Electrical rules checker system and method for reporting problems with tri-state logic in electrical rules checking

An electrical rules checker system and method are provided to appraise tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist. In accordance with one aspect of the invention, the method selects a circuit configuration to be identified. Next, the method identifies any of the circuit configurations at the node, and identifies any probable circuit configurations at the node. Then the method appraises the circuit configurations and the probable circuit configurations. In accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist. A fourth code segment appraises the identified circuit configurations and probable circuit configurations.

Electrical rules checker system and method providing quality assurance of tri-state logic

A coupling capacitance analysis logic allows the classification of capacitance in a hierarchical electronic design. The coupling capacitance analysis logic analyzes capacitance between signal lines and other signal lines, and analyzes capacitance between signal lines and the substrate on which the circuitry resides, between signal lines and transistor gates, and between signal lines and diffusion regions. Capacitances associated with child blocks within the hierarchical design are first analyzed and then brought up into higher levels of the design without the need to repeat the analysis performed in the lower level. In this manner, a complex hierarchical design may be effectively and efficiently analyzed. Once the design analysis is complete, the logic of the invention determines the amount of coupling capacitance attributable to each signal in the design with respect to each subject signal. Each signal will be analyzed as the subject signal and each signal affecting the subject signal will be a culprit signal. For each subject signal, the weighted average of all culprit signals is determined by multiplying the rise and fall times of each culprit signal by the coupling capacitance attributable to that culprit signal. This is performed for each culprit signal affecting the subject signal. The total is then divided by the total coupling capacitance between the subject signal and all culprit signals, resulting in the weighted average of all culprit signals affecting the subject signal. All signals in the design are analyzed as the subject signal.

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Ft. Collins, CO, United States of America

John G McBride