Analog Devices,inc.

John G Kenney

Robert Schell

Kimo Tam

Lawrence M DeVito

Faramarz Sabouri

Michael C St Germain

Stuart John McCracken

Wei-Hung Chen

John P Guido

Declan D Dalton

Rahul Vemuri

Jeremy Z Walker

Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Multiphase clock generators with digital calibration

There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.

Programmable delay line with glitch suppression

Systems and methods are provided for optimizing offset compensation in a receiver with multiple offset compensation D/A converters. At each stage where offset cancellation is applied, there is a fan-out of two or more. At the final stage, comparator offset compensation codes are summed and compared against a digital reference. In one version the digital reference is zero. A second implementation has a non-zero digital reference which is the sum of comparator offsets stored from start up. The difference between the sum of offsets and digital reference is applied to a digital accumulator. The most significant bits of the digital accumulator are applied to a digital D/A converter, which cancel analog offsets in an intermediate stage of amplifiers. The summation of offsets feeding into an accumulator is implemented for all preceding stages.

Nested feedback for offset cancellation in a wireline receiver

Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.

Phasing detection of asynchronous dividers

An apparatus is described and includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D/A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for computing a difference between a first state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a high voltage and a second state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a low voltage.

Techniques for measuring slew rate in current integrating phase interpolator

An apparatus is described and includes a current integrating phase interpolator core having a programmable bias current; an AC-coupled inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D/A) converter for setting an input common mode voltage of the AC-coupled inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a rectangular wave clock signal output from the AC-coupled inverter circuit; and a circuit for computing a difference in the DCD of the rectangular wave clock signal when the input common mode voltage of the AC-coupled inverter circuit is set to a high voltage and when the input common mode voltage of the AC-coupled inverter circuit is set to a low voltage.

Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.

Apparatus and methods for clock and data recovery

A method for calibrating a clock and data recovery circuit may include configuring a phase detector as a bang-bang phase detector. The bang-bang phase detector may be used to determine a phase difference between a sampling clock provided by an interpolator and a calibration signal. The phase detector may also be configured as a linear phase detector. While using the linear phase detector, a linear phase detector parameter may be adjusted such that the phase difference between the calibration signal and the sampling clock is zero, while keeping the phase of the sampling clock fixed.

Method of static phase offset correction for a linear phase detector

Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.

Apparatus and methods for quadrature clock signal generation

A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.

Continuous-rate clock recovery circuit

Apparatus and methods for clock and data recovery are disclosed. In one embodiment, a clock and data recovery system includes a sampler, a deserializer, a phase detector and a frequency detector. The sampler may be configured to sample a serial data stream to produce data samples and transition samples. The deserializer may be configured to deserialize the data samples and the transition samples to produce deserialized data samples and deserialized transition samples. The deserialized data samples and the deserialized transition samples can be aligned and provided to the phase detector and the frequency detector, thereby improving phase alignment and cycle slip detection.

Apparatus and method for clock and data recovery

Apparatus and methods for rotational frequency detection are disclosed. In one embodiment, a rotational frequency detector is configured to receive samples taken from a serial data stream and to generate a frequency up error signal or a frequency down error signal. The rotational frequency detector processes a first set of samples to generate first transition data, which may be stored in a memory. The rotational frequency detector processes a second and third set of samples to generate second and third transition data. The frequency up or frequency down error signal is generated based at least partly on the first, second or third transition data. This configuration can reduce the maximum operating frequency of the rotational frequency detector, thereby simplifying the rotational frequency detector design to a point that a conventional static digital CMOS circuit design flow can be used to design the rotational frequency detector.

Apparatus and method for rotational frequency detection

A transceiver system is disclosed for use in a telecommunication system. The transceiver system includes a transmission circuit including a transmitter input coupled to an input of a transmission amplifier, a receiver circuit including a receiver output coupled to an output of a receiver amplifier, and a transmission line interface circuit that is coupled to an output of the transmission amplifier and to an input of the receiver amplifier. The transmission line interface circuit includes a matching impedance that is directly coupled to a feedback path of the transmission amplifier and that terminates the transmission line of the transceiver system.

Line interface with gain feedback coupled matching impedance

A frequency acquisition system for a tunable oscillator is provided that generally includes a frequency-locked loop circuit including a detector system, responsive to the frequency of an output signal of a tunable oscillator and the frequency of a reference signal, to provide a digital output signal representative of a difference in frequency between the output signal and the reference signal, a register circuit for storing a value representative of the present control state of the tunable oscillator; and an accumulator circuit responsive to a value representative of the present control state of the tunable oscillator and to the digital output signal for providing an updated value for adjusting the frequency of the tunable oscillator towards the frequency of the reference signal.

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Princeton Junction, NJ, United States of America

John G Kenney