Intel Corporation

Apple Inc.

John G Kauffman

Udo Schuetz

Krzysztof Dufrene

Francesco Conzatti

Patrick Torta

Marco Bresciani

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

Apparatus for overload recovery of an integrator in a sigma-delta modulator

An apparatus is provided which comprises: a differential input amplifying stage including a current source and a first node; a first matched pair of transistors coupled to the first node, wherein one of the transistors of the first matched pair is coupled to an output node of a driving stage; a second matched pair of transistors coupled to a second node to bias the second matched pair of transistors, wherein one of the transistors of the second matched pair of transistors is coupled to the output node of the driving stage, and wherein the second node is to be charged according to a first bias of the current source; and a resistive device coupled to the first and second nodes.

Low supply Class AB output amplifier

Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

Apparatus for correcting linearity of a digital-to-analog converter

Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

Sigma-delta analog-to-digital converter including loop filter having components for feedback digital-to-analog converter correction

Low supply class AB output amplifier

Some embodiments include apparatus and methods using a first stage including an integrator, a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series with the first capacitor between an input node and an output node of the amplifier, a quantizer coupled to the output node of the amplifier, and a feedback path coupled to an output node of the quantizer and to the first and second stages, the feedback path including a digital-to-analog converter (DAC), the DAC including an input node coupled to the output node of the quantizer and an output node coupled to the input node of the amplifier.

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Munich, Germany

John G Kauffman