Sony Corporation

Independent Broadcasting Authority

Other

John G Ive

James Hedley Wilkinson

John L Baldwin

Alan C Thirlwall

Robert A Bellis

Mark C Collins

Peter C Boreland

David M Creed

A method of recording and reproducing a digital video signal, the method comprising recording the video signal in oblique tracks on a magnetic tape using a four-head digital video tape recorder, the four heads being arranged in two head pairs disposed on diametrically opposite sides of a rotary head drum, and the video data relating to each field being distributed evenly between the four heads for recording, each oblique track comprising two half-tracks separated by a central gap in which audio data may be recorded, and each field occupying a plurality of successively recorded pairs of half-tracks with each field boundary located at a central gap, and reproducing the video signal at a speed different from the normal reproduction speed using dynamic tracking by successively reproducing two half-tracks from the first part of a first pair of adjacent oblique tracks, then jumping to reproduce two half-tracks from the second part of a second pair of adjacent oblique tracks adjacent to the first pair and so on until all the data of one field has been reproduced, and then jumping to another field.

Digital video recording

A digital video tape recorder comprises a head drum, four transducer heads mounted in pairs on the head drum for recording oblique tracks on a magnetic tape, a demultiplexer for distributing digital data to be recorded and corresponding to a video signal such that each field of the video signal is divided into 50-line segments, the digital data corresponding to each field are evenly distributed between all four of the heads for recording, and each track comprises a block of digital data relating to one 50-line segment and a block of digital data relating to another 50-line segment, the two blocks of digital data being separated by an edit gap.

Digital video recorder having data distribution among four heads

A digital video tape recorder comprises a rotary transducer head arrangement comprising an advance read head and a confidence head both capable of reading audio signals recorded in portions of oblique tracks on a magnetic tape, the heads being positioned relative to one another such that an audio signal at any given position on the magnetic tape reaches the advance read head a predetermined time before the same signal reaches the confidence head, and a delay device for delaying the output of the advance read head by that predetermined time.

Video tape recorders

Apparatus for concealing errors in a digital television signal comprises delay elements for deriving a current sample value and a first group of the sample values spatially closest to the current sample value in the same frame of the television signal and delay elements for deriving from the preceding frame of the television signal a delayed sample value corresponding in position to the current sample value and a second group of sample values respectively corresponding in position to the sample values. The current sample value and the delayed sample value are checked for error, and subtractors check pairs of sample values corresponding in position in the current and preceding frames of the television signal for error, derive a measure of the difference in the levels of the sample values in each pair, and combine the results of these checks to provide an output signal which is a measure of the number of the errors and of the sum of the differences. A threshold device checks the output signal against a predetermined threshold level corresponding to an acceptably small number of errors and a relative low degree of movement in the part of a television picture corresponding to the groups of sample values, and a selector is operative, if the sample value is in error, the delayed sample value in not in error, and the output signal is below the predetermined level, to replace the current sample value by the delayed sample value for supply to an output, and, in all other cases, to supply the current sample value to the output.

Error concealment in digital television signals

A method of correcting errors in binary data which may represent a digital television signal, comprises assembling the data into a plurality of first blocks, each first block comprising a first plurality of, say sixty, data words and a second plurality of, say six, check words and further assembling the first blocks into arrays of first blocks and deriving first and second check blocks for each array of the first blocks. Each check word is derived in dependence on all the data words in the first block and each other check word in the first block. One check word may be derived by modulo-2 addition and the remaining check words may be derived by respective primitive polynomial generators. The first check block is derived by modulo-2 addition and the second check block is derived by a primitive polynomial generator.

Correcting errors in binary data

Digital television apparatus comprises a field store arrangement comprising first, second and third field stores each capable of storing digital signals relating to one field of a television signal, circuit to supply a digital television signal at a variable rate to the field store arrangement, a write control device to supply the digital television signal to one or to two of the field stores for writing therein, depending on the rate of supply of the digital television signal, and a read control device to read the stored digital television signal from one or from two of the field stores, depending on the rate of supply of the television signal, no field store being written into at the same time that it is read from, and the write control device rotating the writing and reading around the field stores cyclically.

Digital television apparatus

A method of detecting and correcting errors in digital audio signals comprises assembling digital data words each of which corresponds to a digital audio signal representing an analog audio sample into units of six data words, assembling with each unit six redundant words derived by exclusive-OR operations on the data word in each row and each column of the unit, assembling the data words and redundant words into sub-blocks and adding cyclic redundancy check code words to the sub-block, recording and reproducing each sub-block, after reproduction using the code words of each sub-block to set the logic state of error flags that have been added to each word in the sub-block, re-forming the units and assembling with each reproduced unit horizontal and vertical syndromes derived by exclusive-OR operations on the data words and redundant words in each row in each column of the unit, comparing the horizontal and vertical syndromes and resetting the logic state of the error flags in dependence on this comparison, deriving further horizontal syndromes by exclusive-OR operations on the data words and redundant words in each row of the reproduced unit and where there is only a single word in a row flagged as being in error, correcting that error word using the further horizontal syndrome, and deriving further vertical syndromes by exclusive-Or operations on the data words and the redundant word in each column of the reproduced unit and where there is only a single word in that column in error, correcting that error word using the further vertical syndrome.

Detecting and correcting errors in digital audio signals

A sequential data block address processing circuit for deriving address signals in dependence on incoming data which comprises sequential blocks of data each including an address signal representing a number, the numbers changing cyclically from block to block, for example where the incoming data is derived from a video tape recorder and represents video information comprising sequential blocks of data each representing a horizontal line scan of video information and each including a line address signal, the circuit comprising an address counter to generate output address signals corresponding to the incoming address signals and likewise changing cyclically from block to block under control of a signal derived from an oscillator and supplied by way of a counter operating as a frequency divider, and an arrangement formed by three latch circuits, an add and delay device, a line address comparator, and a counter for synchronizing the output address signals relative to the incoming address signals only when a predetermined plurality of the incoming address signals have been correctly received.

Sequential data block address processing circuits

Blocks of data, each representing ninety-six lines of a digital television signal are subjected to horizontal shuffling within each line and then to vertical shuffling within each block. The effect of the vertical shuffling is to displace sample words to different lines so that in the event of errors occurring during recording and reproduction in a video tape recorder, valid sample words are available adjacent to any error sample word for the purpose of error concealment. The vertical shuffling does not interfere with vertical parity generation or with the correction of errors after reproduction using the vertical parity words.

Data processing

Apparatus for example for use in achieving correct field framing on reproduction of a digital television signal from a video tape recorder, by correcting errors in an input square-wave signal which signal alternates between first and second levels every four fields of the television signal, the apparatus comprising first and second similar counters to be supplied with the input signal so as to be enabled to count when the input signal is of the first and said second level respectively, means to detect errors in the input signal and thereupon to supply a signal to disable both the first and second counters, a clock pulse source for supplying a clock pulse signal of high frequency relative to the frequency of the input signal to the first and second counter, and a bistable circuit arranged to be triggered to a first stable condition by an overflow signal from the first counter and to a second stable condition by an overflow signal from the second counter, whereby the bistable circuit supplies a corrected replica of the input signal.

Signal error detecting

A random access memory arrangement for reading data out of and into a random access memory asynchronously, for example, to effect time base correction of a digital television signal, comprises a random access memory having common read and write data terminals, an input circuit for supplying input data to said read and write data terminals for writing in the random access memory, a first output latch circuit connected to the read and write data terminals, a second output latch circuit connected to the first latch circuit, and means for supplying control signals to enable the random access memory to write the input data therein at given addresses in synchronism with write pulses of a write pulse signal, to enable the random access memory to read output data from given addresses therein in synchronism with read pulses of a read pulse signal, the read pulse signal being asynchronous with the write pulse signal, to control the first output latch circuit to hold and to supply to the second output latch circuit data supplied to the first latch circuit immediately prior to each write pulse, and to pass therethrough to the second latch circuit data supplied to the first latch circuit at all other times, and to control the second latch circuit to hold the data supplied to it by the first latch circuit immediately prior to the beginning of each read pulse until the beginning of the next succeeding read pulse and to supply the data so held to an output of the arrangement.

Random access memory arrangements

Apparatus for extracting synchronizing information from an incoming serial-bit digital television signal formed of a sequence of data blocks, each block formed of N n-bit words and including within each block a predetermined serial group of m bits forming the synchronizing information, which identify each block of information and enable de-serialization of said signal. The apparatus comprises a first m-stage shift register through which the incoming digital signal is stepped at the bit rate of the incoming digital signal, and which supplies a pulse whenever it holds a predetermined serial group of m bits, a frequency divider to derive from the incoming digital signal a word rate clock pulse signal. Additionally, the apparatus comprises an n-stage shift register through which each said pulse is stepped at the bit rate of the incoming digital signal, a latch circuit synchronized with the word rate clock pulse signal to derive n-bit phase words the bits of which correspond respectively to the conditions of the n stages of the shift register, comparators comparing each phase word with at least one other phase word delayed N or an integral multiple of N word periods of an earlier incoming digital signal. Comparators supply a control signal only when at least one of the comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, wherein the position of this bit in the phase words indicates the phasing of the word rate clock pulse signal relative to the words of the incoming digital signal. In addition, circuits are provided to deserialize the incoming digital signal into parallel-bit n-bit words under control of the control signal.

Synchronization word extractor

A method of processing binary data, which is preferably a digital television signal, comprises dividing the data into blocks of ten 8-bit words, deriving an 8-bit parity word each digit of which is a parity digit for the corresponding digits of the ten words, deriving an 8-bit check word by binary summing the ten words and forming the check word as the eight least significant bits of the resulting binary sum, subjecting to further processing, for example by magnetic recording and reproduction, the block of words including the parity word and the check word, and thereafter checking the parity word and the check word to reveal errors occuring in the ten words during the further processing.

Processing binary data

Digital recording and reproducing apparatus is disclosed for recording digital signals in such a manner as to conceal errors contained therein, including a write address generator for storing incoming digital signals in a first sequence in a memory, and a read address generator for causing the signals to be read out from the memory in a second sequence different from the first sequence. A control device selectively connects the write address generator and the read address generator sequentially to the memory, whereby the digital signals read out from the memory may be recorded on a recording medium.

Recording of digital signals

A circuit for monitoring digital data comprises a shift register for receiving the data to be monitored, the outputs of the shift register being fed either directly to the inputs of memory devices or via controllable gates. The memories are programmed to detect the number of logical `ones` present in the shift register, and the detected number is compared with a reference to determine whether the data should be accepted or rejected. In one mode of operation, the controllable gates alter the inputs to the memories such that they are all the same when the correct data is in the shift register. In another mode of operation, the gates supply the memories with unaltered data and the circuit can detect errors because the data is coded in such a manner that each block of data should contain the same number of digits and the same number of logical `ones`.

Growing community of inventors

London, United Kingdom

John G Ive