Raytheon Company

John G Heston

David D Heston

Mikel J White

Jon Mooney

Scott Mitchel Heston

Ian S Robinson

James R Toplicar

Brian P Helm

James M Carroll

Robert S Isom

Brandon William Pillans

Ethan Santosh Heinrich

Samuel Doug Tonomura

Chad E Patterson

Gordon R Scott

Michael M Fitzgibbon

Claire E Mooney

Tiffany E Cassidy

William Sheridan Kopp

Thomas L Middlebrook

Anthony M Petrucelli

Cynthia Y Hang

David R Fletcher

Richard G Pierce

John R Stanton

Thomas L Iii Middlebrook

An HPA MMIC assembly includes a MMIC device coupled to a thermal spreader. A ground plane is provided on the thermal spreader and coupled to FETs in the MMIC device. The multiple levels of metal separated by multiple dielectric layers provide low-loss broad-band microstrip circuits. The thermal spreader may include diamond, an air/wire-edm spreader or a multi-layer board (MLB) with heat sink vias and ground vias.

Heterogeneous multi-layer MMIC assembly

Guanella topology balun/unun impedance transformer contains cascaded, i.e., series-coupled, coils of different sizes implemented in RF CMOS technology. The cascading of differently-sized coils provides for a large resonance-free operating bandwidth. The shunt inductive loading maximizes low frequency performance.

CMOS Guanella balun

An analog-to-digital conversion system includes two quantizers having a least significant bit arranged in a parallel pair. An input circuit coupled to the quantizers provides an analog input signal to the quantizers. A dither generator coupled to the quantizers provides an analog differential dither signal for perturbing quantization of the analog input signal. A combiner coupled to the quantizers adds respective outputs of the quantizers to obtain a linearized digital representation of the analog input signal.

Analog to digital conversion using differential dither

A system and method of converting an analog input signal to a digital output signal includes coupling an analog input signal to a plurality of analog-to-digital converters (ADCs) arranged in a parallel configuration. Pseudo-random discrete valued complementary offset voltage levels that span an input voltage range of the sum of the plurality of ADCs are generated. An amount of continuous, analog dither that randomly varies at values between the discrete offset voltage levels is generated, the analog dither being less than steps between the discrete offset voltage levels. On different clock cycles, different discrete offset voltage levels are coupled to at least some of the ADCs. At each ADC, the respectively coupled analog input, discrete offset voltage level, and continuous analog dither are quantized to obtain a digital output. The respective digital outputs are combined to obtain a linearized digital representation of the analog input signal.

Complete complementary code parallel offsets

An integrated circuit system having: (A) a semiconductor chip with a signal strip conductor disposed on an upper surface of the chip; an active semiconductor device disposed of the upper surface of the chip electrically connected to the signal strip conductor; and a first ground plane conductor disposed on a bottom surface of the chip disposed under the signal strip conductor; and (B) a support structure having: a second ground plane disposed over, and separated from, the signal strip conductor by a dielectric region between the second ground plane and the signal strip conductor on the chip; a signal contact disposed on the bottom surface of the support structure displaced, electrically insulated, from the second ground plane conductor, and electrically connected to a portion of the signal strip conductor. The signal strip conductor, the first ground plane conductor, and the second ground plane conductor provide a stripline microwave transmission line.

Integrated circuit system having stripline structure

In an improved T/R switch configuration of a radio transceiver, the sizes of active switches coupled in series between the receive port and the common port are tapered such that the voltage referenced to ground across the active devices of the T/R switch is more evenly distributed among the switches which increases the power handling capability of that path. According to one embodiment of the present invention, an RF switch includes a plurality of first switches coupled in series between a transmit port and a common port for transmitting an RF signal, and a plurality of second switches coupled in series between a receive port and the common port. At least two of the plurality of second switches have different sizes such that the at least two of the second switches have substantially the same nodal impedance with respect to a frequency of the RF signal and an RF ground.

High power RF switch with active device size tapering

A power amplifier includes a transistor, a transmission line transformer, and a capacitor. The transistor is operable to receive a signal and to generate an amplified signal. The transistor has a source, a drain, and a gate. The gate has a first impedance and is operable to receive the signal to be amplified. The transmission line transformer has a first, second, third, and fourth port, the first port and the third port being coupled directly to the gate of the transistor, and the fourth port being coupled to a source device having a second impedance. The capacitor has a first end and a second end. The first end of the capacitor is coupled to the second port of the transmission line transformer and the second end is coupled to a ground.

Method and system for amplifying a signal using a transformer matched transistor

A power amplifier includes a transistor, a transmission line transformer, and a capacitor. The transistor is operable to receive a signal and to generate an amplified signal. The transistor has a source, a drain, and a gate. The gate has a first impedance and is operable to receive the signal to be amplified. The transmission line transformer has a first, second, third, and fourth port, the first port being coupled to the gate of the transistor and the third port, and the fourth port being coupled to a source device having a second impedance. The capacitor has a first end and a second end. The first end of the capacitor is coupled to the second port of the transmission line transformer and the second end is coupled to a ground.

In accordance with the teachings of the present invention, a method and apparatus for increasing the efficiency of electrical systems are provided. In a particular embodiment, the apparatus comprises a first electrical component including a self-biasing resistor and at least one input terminal coupled to a power supply, and a second electrical component including at least one input terminal coupled to an output terminal of the first electrical component, and an electrical short circuit connected across the self-biasing resistor in the first electrical component such that current from the power supply bypasses the self-biasing resistor.

Method and apparatus for increasing efficiency of electrical systems

According to one embodiment of the invention, a power absorber for receiving a signal having a fundamental frequency includes an input node for receiving the signal and a first PIN diode circuit having a first end electrically connected at the input node and a second end. The first PIN diode circuit includes at least one PIN diode. The absorber also includes a load resistance having a first end electrically connected to the second end of the PIN diode circuit and a second end electrically connected to a reference voltage. The absorber also includes a quarter wave transmission line having a first end electrically connected to the input node at a second end. The quarter wave transmission line has an electrical link that is one quarter of the wavelength of the fundamental frequency. The power absorber also includes a second PIN diode circuit having an input electrically connected to the second end of the quarter wave transmission line and an output electrically connected to the reference voltage. The first choke is provided in parallel with the load resistor.

Power absorber system and method

A power amplifier includes amplifier stages. An amplifier stage includes a transistor, and at least one amplifier stage comprises a driver stage. The amplifier stages include a first amplifier stage having a first transistor and associated with a first output power, and a second amplifier stage having a second transistor and associated with a second output power. A current sharing coupling couples the first amplifier stage and the second amplifier stage. The first amplifier stage and the second amplifier stage share a current through the current sharing coupling. The current sharing coupling facilitates scaling of the first output power and the second output power.

Amplifying a signal using a current shared power amplifier

An apparatus includes a circuit having first, second and third circuit portions, the first and third circuit portions each including at least one semiconductor circuit component. The second circuit portion includes at least one non-semiconductor circuit component, and is free of semiconductor circuit components. A first substrate has the first and second circuit portions disposed adjacent one side thereof. A second substrate is physically separate from the first substrate, and has the third circuit portion disposed adjacent a side thereof which faces the one side of the first substrate. The second and third circuit portions have electrically conductive parts which are coupled by thermo-formed bonds.

Method and apparatus for combining multiple integrated circuits

According to one embodiment of the present invention a method for biasing a power amplifier having at least one transistor exhibiting kink anomaly includes providing a bias circuit coupled to a gate of at least one transistor of the power amplifier. The method also includes providing, by the bias circuit, a bias voltage to the gate. The bias circuit has a load characteristic that intersects a current versus gate voltage curve for the gate at a frequency of operation of the power amplifier only once and that exhibits a low impedance at the intersection of the load characteristic with the current versus gate curve of the gate.

Method and system for biasing power amplifiers with kink anomaly

A switch circuit includes a first electronic switch coupled between two terminals, and a second electronic switch and a capacitor coupled in series between a reference voltage and a control input of the first electronic switch. A different switch circuit includes first and second electronic switches coupled in series between two terminals with a further terminal coupled to a node between the switches, a third electronic switch and a first capacitor coupled in series between a reference voltage and a control input of the first electronic switch, and a fourth electronic switch and a second capacitor coupled in series between a reference voltage and a control input of the second electronic switch.

Method and apparatus for electronic switching with low insertion loss and high isolation

A multi-stage amplifier for amplifying radio frequency signals includes a first amplifier stage having a first transistor and a second amplifier stage having a second transistor. The first transistor includes a first drain connected to a reference voltage through a first connection circuit. The second transistor includes a second drain connected to a reference voltage through a second connection circuit. The amplifier also includes a first transmission line connecting a portion of the first connection circuit to a portion of the second connection circuit and a resistive element connected in parallel with the first transmission line between the portion of the first connection circuit and the portion of the second connection circuit. The resistive element suppresses oscillation conditions at either of the first and second bias terminals.

Growing community of inventors

Murphy, TX, United States of America

John G Heston