Intel Corporation

Hiel Corporation

John G Gierach

Tomer Bar-On

Hugues Labbe

Travis T Schluessler

Gabor Liktor

Andrew T Lauritzen

Devan Burke

Abhishek Venkatesh

Abhishek R Appu

Altug Koker

Prasoonkumar Surti

Joydeep Ray

Balaji Vembu

Ankur N Shah

Kai Xiao

Thomas F Raoux

Subramaniam M Maiyuran

Guei-Yuan Lueh

David M Puffer

Karthik Vaidyanathan

Michael Apodaca

John H Feit

Elmoustapha Ould-Ahmed-Vall

Nikos Kaburlasos

Jacek Kwiatkowski

Adam T Lake

Eriko Nurvitadhi

Carsten Benthin

Peter L Doyle

Amit Bleiweiss

Sven Woop

Philip R Laws

Peng Guo

Oguz Hasan Elibol

Jorge F Garcia Pabon

Dhawal Srivastava

Anil Thomas

Gokce Keskin

Pawel Majewski

Daniel Walsh

Darrel K Palke

Won-Jong Lee

Srividya Karumuri

Wojtek Rajski

Jeremy Brennan

Tomer Bar On

Pruthvi Gowda Thorehosur Appajigowda

Nishant Patel

Huma Abidi

Jaikrishnan Menon

David Puffer

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.

Out-of-order pixel shading and rasterization

Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

Topology shader technology

An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Graphics anti-aliasing resolve with stencil mask

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

Compute optimization mechanism for deep neural networks

Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.

Techniques to manage execution of divergent shaders

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

GPU mixed primitive topology type processing

Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading

Growing community of inventors

Hillsboro, OR, United States of America

John G Gierach