Adv Antest Corporation

Verigy (singapore) Pte. Ltd.

John Frediani

Mei-Mei Su

Phillip D Burlison

Ben Rogel-Favila

Shunji Tachibana

Andrew Niemic

The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

Method and system for acquisition of test data

The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.

Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs. Each of the plurality of hardware accelerator circuits comprises a pattern generator circuit configurable to automatically generate test pattern data and a comparator circuit configured to compare data.

Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block

A method for testing using an automated test equipment is presented. The method comprises transmitting instructions for performing an automated test from a system controller to a tester processor, wherein the instructions comprise parameters for a descriptor module. The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor. Further, the method comprises interpreting the parameters from the descriptor module using the reconfigurable circuit, wherein the parameters control execution of a plurality of test operations on a DUT coupled to the instantiated FPGA block. Additionally, the method comprises constructing at least one packet in accordance with the parameters, wherein each one of the at least one packet comprises a command for executing a test operation on the DUT. Finally, the method comprises performing a handshake with the DUT to route the at least one packet to the DUT.

Tester with acceleration for packet building within a FPGA block

As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain.

Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test

A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.

Dynamic mask memory for serial scan testing

An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns.

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Corralitos, CA, United States of America

John Frediani