Intel Corporation

Oracle International Corporation

John Fernando

Ramesh V Peri

Ravi Kolagotla

Srinivas P Doddapaneni

Ravi Kolagotia

Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Mutual exclusion in a non-coherent memory hierarchy

A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores.

Memory paging for processors using physical addresses

A memory addressing technique using load buffers is described. More particularly, embodiments of the invention relate to a method and apparatus for accessing data in a computer system by exploiting addressing mode information within an instruction such that if present, data may be obtained from the load buffers, rather than accessing a cache memory or other memory device within the computer system.

Virtualized load buffers

In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.

Accessing data from different memory locations in the same cycle

A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Growing community of inventors

Austin, TX, United States of America

John Fernando