International Business Machines Corporation

John Fenton Scanlon

Peter H Gum

Donald W McCauley

Leslie W Wyman

Casper A Scalzi

Roger E Hough

Mark S Farrell

Moon Jung Kim

Moon Ju Kim

Barry Watson Krumm

Karl J Duvalsaint

Francis E Johnson

Terry L Borden

John C Rathjen, Jr

James C Mazurowski

George H Bean

Norman C Chou

Mark E Rakhmilevich

A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system. A control program being executed in its data processing system to reconfigure storages that are assigned to guests when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space. Memory can be reconfigured by a control program that allows main storage, and expanded storage associated with a guest's real storage to be mapped to multiple discontiguous areas of host absolute spaces. When sufficient real addressing is not available in the host absolute addressing space it allows expansion of the host absolute storage space that maps a guest storage. The system can be used in scalar, parallel and massively parallel computer systems having plural logical processors (LPARs).

Multi-zone relocation facility computer memory system

A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

CPU expansive gradation of I/O interruption subclass recognition

The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems. The logical CPU(s) of the guests are dispatched on one or plural real CPUs in the system using the S/370XA SIE (start interpretive execution) instruction. Special operations are provided, including the CPU alerting of other guests in different partitions using I/O interruption signalling. Interception is provided to handle special circumstances.

Logical resource partitioning of a data processing system

Growing community of inventors

Hyde Park, NY, United States of America

John Fenton Scanlon