International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

John Farley Ewen

Matthew James Paschal

Joseph M Mosley

Mehmet Soyuer

Steven Mark Clements

Giri N K Rangan

Stephen Charles Wilkinson-Gruber

Hayden C Cranford, Jr

John Francis Bulzacchelli

Clint Lee Schow

John D Davis

Herschel Akiba Ainspan

William K Hogan

Mounir Meghelli

Albert X Widmer

David W Siljenberg

Matthew B Baecher

Ahmed Mostafa

Min Wu

Saila Ponnapalli

Carl J Anderson

Kevin Paul Demsky

Gautam Gangasani

Allan L Mullgrav, Jr

Davide Visani

Edward F Culican

Umesh Kumar Shukla

Philip E Pritzlaff, Jr

Trushil N Shah

Kenneth Paul Jackson

Michael William Marlowe

Rajesh Cheeranthodi

Sarabjeet Singh

Mehedi Hasan

Santhosh Madhavan

Shridha Tyagi

Arun R Umamaheswaran

Clarence I Peterson, Jr

Philip F Noto

Scott A Mc Cabe

Amar Chandra Mahadeo Dwarka

An analog-to-digital converter-based serial receiver configured to tune analog equalization settings for link training is described. An analog signal from a transmitter is received and the receiver applies initial analog equalization settings. The receiver then converts the equalized analog signal into a digital signal. The receiver then measures frequency content of the analog signal and saturation at the analog-to-digital converter and determines updated analog equalization settings.

Adaptive analog equalization in ADC-based receiver

Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.

Generating a parallel data signal by converting serial data of a serial data signal to parallel data

Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.

Calibration of sampling phase and aperature errors in multi-phase sampling systems

Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.

Generating negative impedance compensation

A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.

Bias circuit for a MOS device

An analog error amplifier includes an amplifier circuit and a replica bias circuit that together produce an output signal representing a difference between an input signal and a reference signal. The amplifier circuit produces the output signal in response to the input signal and a bias signal provided by the replica bias circuit. The bias signal may establish a reference threshold of a basic amplifier in the amplifier circuit. The replica bias circuit produces the bias signal in response to the reference signal and drives the bias signal to be equal to the reference signal. The replica bias circuit may include a plurality of amplifier stages. The bias signal produced by a single replica bias circuit may be provided to a plurality of amplifier circuits to provide a plurality of error amplifiers for a single reference signal.

Low-voltage CMOS error amplifier with implicit reference

A switchable bandwidth optical receiver is implemented in a front-end of the receiver in at least one of three ways. A switchable impedance may be provided at the input to a preamplifier of the front end, the preamplifier of the front-end may have a switchable impedance therein, and/or a switchable filter may be provided at an output of the preamplifier.

Switchable-bandwidth optical receiver

Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels and configured to receive the half-rate clock signal. Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting test pattern and half-rate clock signals to one or more corresponding receiver channels; and detecting error utilizing one or more error detection circuits connected to receive the half-rate clock signal.

Architecture for built-in self-test of parallel optical transceivers

An output buffer provides a stable, predetermined low voltage differential over power supply, temperature, and process variations yet has a high speed of operation. More particularly, a data path of an output buffer includes an emitter-coupled differential amplifier followed by an output section of two level-shifting emitter followers. A predetermined operating current biases the differential amplifier for unsaturated operation and a reference current biases the output section for unsaturated operation. The data path remains unencumbered by compensation circuitry to preserve high speed operation. Instead, a voltage compensator biases the differential amplifier to compensate, at least in part, for variations in a supply voltage. In addition, a variable biasing current to the voltage compensator with a predetermined temperature coefficient may further temperature compensate the differential amplifier. In addition to such &ldquo;upstream&rdquo; compensation, the output buffer may further include &ldquo;downstream&rdquo; temperature compensation by the addition of a V,multiplier circuit to the reference current biasing of the output section. Additional temperature and level-shifting compensation may also be achieved through cascading a plurality of buffer stages.

High-speed fully-compensated low-voltage differential driver/translator circuit arrangement

The constant current source circuit provides current that compensates for changes in performance resulting from changes of temperature. The circuit mixes variable amounts of current having a negative temperature coefficient with current having a positive temperature coefficient. Analog and digital embodiments of the circuit are disclosed. In the analog embodiment, the amount of current having a positive temperature coefficient is added to an amount of current having a negative temperature coefficient as determined by the voltage difference between a variable control voltage input to transistors and a bandgap reference voltage. A transistor in each of two current selectors is connected to the variable control voltage, one of which is connected to ground and the other of which is output; and another transistor in each current selector is connected to the reference voltage, and again one transistor is grounded and the other is output whose current is mixed with the output from the transistor in the first current selector connected to the variable control voltage. A continuous range of temperature coefficients are realizable by varying the control voltage with respect to the bandgap reference voltage. The digital embodiment has a digital-to-analog converter connected to a bias voltage from the current having a positive temperature coefficient and a second digital-to-analog converter connected to a second bias voltage from the current having a negative temperature coefficient. A digital input signal to a corresponding switch determines if its respective transistor in each of the digital-to-analog converters conduct current. The two digital-to-analog converters may be configured in a common centroid arrangement of integrated complementary unit cells. The constant current source circuit can be used to drive off-chip parallel loads such as VCSELs.

Constant current source circuit with variable temperature compensation

A method of designing a high Q inductor for implementation in multiple metalization levels in conventional integrated circuit technology uses a software assisted iterative technique to achieve a design Q factor. The inductor turns utilize the multiple metalization levels to reduce inductor resistance.

Method for designing high-Q inductors in silicon technology without

A novel bias generator circuit for a voltage controlled oscillator is described. The bias generator allows the VCO frequency to be made essentially independent of the supply voltage and temperature.

VCO bias circuit with low supply and temperature sensitivity

The present invention is a translator circuit which receives an input compatible with a differential current switch type of circuit and transmits an output compatible with a super buffer logic type of circuit. The translator circuit has a gain stage interposed between an input and output stage which both level shift the signal downward. The gain stage provides the translator circuit with the performance necessary to avoid attenuation of the signal between receiving the input signal and transmitting the output signal. The input and output stages buffer the gain stage by shifting the voltage level of the translator downward in two stages. The translator circuit provides its own voltage reference circuits which are compatible with the power supply of the DCS and SBL circuits. The reference circuits are self compensating for temperature effects. The translator circuit of the present invention allows different types of circuit families to be inexpensively designed on the same integrated circuit chip. Therefore, DCS type circuits can be used to implement high performance operations and SBL circuits can be used to implement complex logic circuits in an efficient design. The translator circuit is used in a light receiver, including a photodetector for converting a light signal into an electrical signal. The photodetector is coupled to an amplifier/bias circuit. The amplifier/bias circuit generates a differential signal input for a differential current switch circuit. The differential current switch circuit is connected to a super-buffer logic circuit through the translator circuit.

Differential current switch to super buffer logic level translator

A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the rate of the incoming data. These clocks are sampled by a pair of edge triggered flip-flops using the transitions of the received data as triggers. The outputs of these flip-flops are exclusive OR-ed to provide a signal indicating whether the generated clock leads or lags the received data. The half-speed 1:2 demultiplexer circuit uses the rising and falling edges of a half-speed 90-degree clock to latch the received data through a pair of flip-flops. The outputs of these flip-flops, each triggered by a different edge of the clock, make up two demultiplexed data streams. The clock recovery and demultiplexer circuits of the present invention can be extended to operate at lower clock rates and configured to provide wider demultiplexing.

Half-speed clock recovery and demultiplexer circuit

A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

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Rochester, MN, United States of America

John Farley Ewen