Intel Corporation

John Faistl

Robert S Chappell

David W Burns

Hermann Gartler

Michael D Tucknott

Rajesh S Parthasarathy

Sebastian Winkel

Oleg Margulis

Vineeth Mekkat

Zhongying Zhang

Mark Dechene

Janghaeng Lee

Hou-Jen Ko

Rajesh S Parathasarthy

A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.

Method and apparatus for supporting speculative memory optimizations

A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Method and apparatus for bus lock assistance

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Hillsboro, OR, United States of America

John Faistl