Intel Corporation

Other

Trw Limited

Mcdonnell Douglas Corporation

Key Control Holding, Inc.

Intel Coproration

John F Zumkehr

James E Chandler

Amir A Abouelnaga

Pete D Vogt

Arnaud J Forestier

Darrell S McGinnis

Derek A Thompson

Howard S David

Jeffrey E Smith

Klaus J Ruff

Steve A McKinnon

Renjeng Chiang

Ray I Chiang

John L Bryan

Roger A Niederland

Jeffrey Smith

James Chandler

Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to provide a driver signal to the memory device. In some embodiments, the driver signal is substantially symmetrical around the controllable voltage reference.

Reduced signal level support for memory devices

The object control and tracking system of the present invention includes a computer, a system controller, and at least one object storage drawer housed within a security cabinet. The system controller provides a bi-directional communication link between the computer and a printed circuit board located within the object storage drawer. The objects are symmetrically shaped acrylic key fobs each containing a touch memory device to store information about as set of keys or other valuable objects associated with the fob. A dress plate, incorporating a plurality of slots for interfacing with the fobs, is within the drawer and provides the mechanical support for the key fobs. The key fobs are generally symmetrically shaped to fit into the slot. The slot spacing is staggered in the array so that it is easier for a user to replace or to locate the key fob if the array is almost fully occupied. The slots of the array are symmetrical in nature so that a user can insert the tongue of the key fob in either orientation into the slots of the array. The top side of a PCB board is in immediate contact with the bottom side of the dress plate. Symmetrical slots are cut through the PCB and are in alignment with the dress panel slots. On the bottom side of the PCB board, each slot contains pairs of downward, vertically extending, biased metal contacts. Each slot incorporates an LED for providing a visual indication to a user of the location of an empty slot or the location of an inserted fob.

Object controlled access and inventory system

In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a receiver pair to receive a differential signal and a reference signal and to generate at least one comparison signal reflecting where a first signal of the differential signal and a second signal of the differential signal cross each other with respect to the reference signal. The second signal is a negative compliment of the first signal. The apparatus further includes a phase detector to determine a phase error based on the at least one comparison signal. The apparatus also includes an edge delay control driver pair to adjust the differential signal based on the phase error.

Calibrated differential voltage crossing

In some embodiments, a system and method for making rank-specific adjustments to the READ tenure parameters of a double data-rate (DDR) memory component to improve the DDR bus timing margins. When a READ tenure is encountered for the DDR memory component, the rank of the DDR memory component is calculated and the value is used to retrieve two adjustment signals, which are specific to the DDR memory component, from the look up table. One of the adjustment signals is used to adjust a gating signal for the data strobe signal of the component. The other adjustment signal is used to fine tune a required &#xbc; clock delay for the data strobe signal to read the data from the DDR memory component while adjusting for the inherent latency of the DDR memory component. Other embodiments are described and claimed.

System and method for dynamic rank specific timing adjustments for double data rate (DDR) components

Embodiments of the invention include a memory controller to interface to memory. In one embodiment, the memory controller includes a pull-up calibration terminal to couple to an external pull-up resistor, a pull-down calibration terminal to couple to an external pull-down resistor, a voltage reference node, a first switch coupled between the pull-up calibration terminal and the voltage reference node, and a second switch coupled between the pull-down calibration terminal and the voltage reference node. The first switch and the second switch may be selectively closed to generate an internal voltage reference on the voltage reference node in a normal mode that may be used for comparison with an input signal to receive data.

Internal voltage reference for memory interface

According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the driver slices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.

Hybrid compensated buffer design

A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Method and device for symmetrical slew rate calibration

A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Two dimensional data eye centering for source synchronous data transfers

Methods, apparatus and machine-readable medium to terminate a memory bus line. In some embodiments, the memory bus line is terminated with one or more transistors of an output buffer that are used to drive the memory bus line during a memory write.

Memory bus termination

A write pointer () from a write pointer circuit () may cause a demultiplexer circuit () to direct data from a memory cell (A&#x2013;N) to a desired bit location () in a register 14. A read pointer () may cause a multiplexer circuit () to select data from a desired bit location in the register to provide as output data () or to select one of the bits of the write pointer. The write pointer may be incremented by a data strobe signal (). The state of the write pointer may be determined by reading the bits of the write pointer, and the write pointer may be synchronized via a reset line ().

Write pointer error recovery

According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the devices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.

A system, method and medium may delay a strobe signal based upon a delay base and a delay adjustment to reduce effects of process variations and/or environmental changes.

System and method for delaying a strobe signal based on a slave delay base and a master delay adjustment

According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first device. The corresponding write data may be delayed by the first device by a first delay period. The one or more write commands and their corresponding write data are stored in a set of buffers. In response to another write command being received from the first device, a buffered write command and its corresponding write data are sent to a second device for execution, without waiting for the write data corresponding to said another write command to be sent from the first device.

Memory control translators

Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Growing community of inventors

Orange, CA, United States of America

John F Zumkehr