Picker International, Inc.

John F Vesel

David C Oliver

Robert A Cecil

Michael J Petrillo

Micheal J Petrillo

James M Kapcio

Pradipa Subramaniam

Fred C Mailey

A DMA control device (10) is connected with an n-bit address bus (12) by way of a bidirectional internal n-bit bus (14). The m most significant bits of signals received on the bidirectional bus (14) are reserved for carrying codes which identify or enable the DMA device to respond, to generate a load signal, to generate a count signal, and to generate an output signal. The remaining bits are reserved for address data. The load signal causes the remaining bit addresses to be loaded into counters (22) or registers (40). The count signal causes the counters (22) or a latched incrementor (44) to increment. The output signal controls three-state buffers (24, 42, 46) which cause the current address to be outputted on the bidirectional bus. In this manner, the DMA control device has only a single bus and in the embodiment of FIG. 2 replaces the counter array with a register array.

Direct memory access control device for use with a single n-bit bus with

Pixel values f(m,n) of an image are reduced (A) by predicting each pixel value based on preceding pixel values and retaining the deviation e(m,n) between the actual and predicted values. The reduced values e(m,n) are serially fed to an input latch (20). A latched sizer (22) determines the larger of the number of bits of the value in the input latch and the largest previously received reduced value e(m,n). A comparator (42) compares a number of bits from the latched sizer with the number of bits per field indicated by a look-up table (44). Each time another reduced value e(m,n) is received, a state counter (46) indexes one state, i.e., increases the number of bit fields per output word and, when necessary causes the look-up table (44) to reduce the number of bits per field. When the comparator (42) determines that the number of bits from the latched sizer will not fit in the bit field size indicated by look-up table (44), a bit shuffler (C) is caused to form a packed word from the precedingly received reduced values. When the number of bits does fit into the bit field, the reduced value in the input latch (20) is forwarded to the bit shuffler and the process repeated with the next reduced value.

Pipelined image data compression system

A network (A) carries large image blocks among medical diagnostic equipment (20, 22, 24), archive computer (26), and data handling and display stations (28, 30). Four kilobyte packets of 4 megabyte image blocks are moved from transmit buffers (38) to queuing buffers (42). The order in which packets from the queuing buffers are transmitted on the network medium (10) is determined by a combination of an assigned priority, duration in the buffer, and a statistical availability of the addressed receiving node. A data link (52) at the receiving node includes an elasticity buffer (122) which stores a small plurality bits, e.g. 5, to accommodate for variances in the clock speed of the transmitting and receiving nodes. A buffer table (60) monitors memory addresses at which preceding data packets corresponding to the same image are stored and provides address information to send each subsequently received packet. Before transmitting the image data packet, the transmitting node data link first sends a query to the receiving node to check availability to avoid the transmission of relatively large data packets to unavailable nodes. Each transmitting node normally passes the token after it has transmitted one packet of data. When the transmitting node holds the token for several sequential data packet transmissions, it passes a restricted token which allows the other nodes to transmit high priority small messages that are much smaller than the image data packets.

High efficiency image data transfer network

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Willowick, OH, United States of America

John F Vesel