Hewlett-packard Company

John F Shelton

Kenneth K Chan

William R Bryg

James B Williams

Donald A Williamson

Ehsan Rashid

Michael L Ziegler

Eric R Delano

John R Obermeyer

Ross V La Fetra

A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

Method and apparatus for checking cache coherency in a computer

A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

Apparatus and method for operating chips synchronously at speeds

A rate generator for use in a video server or other computer system requiring the generation of multiple timing signals from a single fixed frequency clock signal is disclosed. The rate generator stores a count value, a subtrahend value and a preload value for each timing signal that must be generated. The subtrahend value is subtracted from the count value. If this causes an underflow, an underflow signal, which comprises the generated timing signal, is asserted. The preload value is then added to the result of the subtraction, forming the new count value. If an underflow did not result from the subtraction, the result of the subtraction is the new count value. The frequency of the generated timing signal is determined by the ratio of the subtrahend and preload values. This permits the generation of many different timing signals from a single fixed frequency. The architecture required to perform these operations is relatively simple and inexpensive.

Programmable rate generator

Clock generating means for generating bus clock and chip clock

A multiple round-robin arbitration scheme for a shared bus system that ensures forward progress by each component utilizing the shared bus. In the shared bus system, component modules arbitrate for control of the bus for one or more cycles, and send transactions on the bus during cycles in which they control the bus. The transactions are divided into a set of transaction classes. Certain classes of transactions cannot be issued during certain bus cycles. In certain other cycles, transactions of any class may be issued. The multiple round-robin arbitration scheme ensures forward progress by ensuring that each module seeking to issue a transaction of a given class obtains control of the bus during a cycle when transactions of that class can be issued.

Multiple arbitration scheme

A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor and to the system memory. The first cache memory contains a subset of data in the system memory. A second cache memory is also connected to the processor. The second cache memory contains a subset of data in the first cache memory. Data integrity in the system memory is maintained using the first cache memory only. Whenever the processor writes data, the processor writes data both to the first cache memory and to the second cache memory. Whenever the processor reads data, the processor attempts to read data from the second cache memory. If there is a miss at the second cache memory, the processor attempts to read data from the first cache memory. If there is a miss at the first cache memory, the data is retrieved from the system memory and placed in the first cache memory. The processor then reads the data from the first cache memory. Generally, when the processor reads data from the first cache memory, the read data is written into the second cache memory.

Computing system with a cache memory and an additional look-aside cache

A multi-way set-associative cache memory stores data in a plurality of random access memories. Data in the multi-way set-associative cache memory is organized in lines of data. The multi-way set-associative cache memory allows access of single words and allows access of multiple-words of a length specific to the multi-way set-associative cache memory. Within the plurality of random access memories, data are placed such that corresponding words of each line of data is placed in different random access memories. Further, each word from each multiple word is placed in different random access memories. For single word access, one word is accessed from one of the plurality of random access memories. For multiple-word access, one word from each of the plurality of random access memories is accessed.

Fast multiple-word accesses from a multi-way set-associative cache memory

A scan testable circuit in a computer system is controlled by using a single scan clock and a fixed delay circuit to realize the required scan clocks and a required scan mode enable signal. The multiple signals are generated from a subset of signals supplied to the scan control signal generation circuit. System data and scan data are routed through a multiplexer to test or initialize lines and circuitry. A scan control signal generation circuit according to the invention has the advantage of eliminating as excess a scan mode enable signal originating elsewhere in the computer system, thereby eliminating unneeded signal traces while minimizing the number of pins required for this function. In a first embodiment, a scan mode enable signal is generated from one of two scan clocks. In a second embodiment, both scan clocks and the scan mode enable signal are generated from a single source clock.

Apparatus for generation of scan control signals for initialization and

A scheme for improving the decoding time of macroinstruction opcodes in a programmed computer is provided. By having a direct Instruction Jump Table responding to macroinstructions and a pipelined Address Jump Table responding to the same macroinstructions simultaneously, larger sequences of microinstructions are decoded in a minimum number of microcycles, thus resulting in a faster operating programmed computer.

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La Selva Beach, CA, United States of America

John F Shelton