Nxp Usa, Inc.

Freescale Semiconductor,inc.

John F Pillar

Bernard Francois St-Denis

Tommi M Jokinen

Bernard Marchand

Michael Kardonik

Mark A Schellhorn

Peter W Newton

William C Moyer

Kun Xu

Adi Katz

David B Kramer

Allen Lengacher

Eric Englert

Tim J Buick

Timothy Buick

A mechanism is provided to maximize utilization of internal memory for packet queuing in network devices, while providing an effective use of both internal and external memory to achieve high performance, high buffering scalability, and minimizing power utilization. Embodiments initially store packet data received by the network device in queues supported by an internal memory. If internal memory utilization crosses a predetermined threshold, a background task performs memory reclamation by determining those queued packets that should be targeted for transfer to an external memory. Those selected queued packets are transferred to external memory and the internal memory is freed. Once the internal memory consumption drops below a threshold, the reclamation task stops.

Method and system for effective use of internal and external memory for packet buffering within a network device

A data processing system can comprise a first module having a workspace and configured to execute a task that can request access to a frame in a system memory, a queue manager configured to store a frame descriptor which identifies the frame in the system memory, and a memory access engine coupled to the first module and the queue manager. The memory access engine copies requested segments of the frame to the workspace and has a working frame unit to store a segment handle identifying a location and size of each requested segment copied to the workspace of the first module. The memory access engine tracks history of a requested segment by updating the working frame unit when the requested segment in the workspace is modified by the executing task.

Systems and methods for frame presentation and modification in a networking environment

Methods and systems are disclosed to access memory locations using auxiliary keys in addition to primary keys. Commands are received by a memory management unit to insert or access records in an exact match keyed lookup table where records include keys (i.e., primary keys), auxiliary keys, and data. When a command to insert a new record is received along with key and data, the memory management unit generates a new unique auxiliary key. The auxiliary key includes a table index generated from the key and a collision index that is unique for any records having the same table index. The key, the auxiliary key, and the data for the new record are then stored within the lookup table along with a collision pointer that links records having the same table index. Subsequently, commands to access the new record can selectively use either the original key or the auxiliary key.

Systems and methods to access memory locations in exact match keyed lookup tables using auxiliary keys

Configurable per-task state counters for processing cores in multi-tasking processing systems are disclosed along with related methods. In part, the disclosed embodiments include a work scheduler and a plurality of processing cores. The work scheduler assigns tasks to the processing cores, and the processing cores concurrently process multiple assigned tasks using a plurality of processing states. Further, task state counters are provided for each assigned task, and these task state counters are incremented for each cycle that the task stays within selected processing states to generate per-task state count values for the assigned tasks. These per-task state count values are reported back to the work scheduler when processing for the task ends. The work scheduler can then use one or more of the per-task state count values to adjust how new tasks are assigned to the processing cores.

Configurable per-task state counters for processing cores in multi-tasking processing systems

A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

System and method for conditional task switching during ordering scope transitions

A method and apparatus are provided for computing a CRC value for a data stream packet with a modified portion and an unmodified portion extending a distance to the end of the data stream packet by computing a first CRC value from the unmodified portion, computing a second CRC value from the modified portion, adjusting the second CRC value based on a shift length equal to the distance of the unmodified portion to compute a perspective shifted second CRC value by using a fixed number of distance lookup table operations, and generating an updated CRC value from the first CRC value and perspective shifted second CRC value, thereby avoiding recalculating a complete CRC value based on an entirety of the data stream packet.

Method of offloading cyclic redundancy check on portions of a packet

A data processing system includes a content addressable memory (CAM). Each entry of the CAM corresponds to a task and is configured to store a current scope of each task. A random access memory (RAM) is configured to shadow information of the CAM. Transition position storage circuitry is configured to store transition age positions for tasks. Control circuitry is configured to, in response to a command to transition a selected task to a destination scope, access the RAM to determine the current scope for the selected task, use the current scope to perform a match determination with the CAM to determine if any entries corresponding to tasks other than the selected task match the current scope; and for any matching entries, updating a transition age position in the transition position storage circuitry for the corresponding task within the current scope.

Systems and methods for order scope transitions using cam

A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations.

Data processor coupled to a sequencer circuit that provides efficient scalable queuing and method

Methods and devices for scanning an incoming datastream for a plurality of target patterns. The scanning system receives an incoming data stream and stores the stream as sequential symbols in a register array. Previously received symbols are shifted in the array as incoming symbols are shifted in. A trigger stage computes a hash value based on the k most recently received symbols. The trigger stage then uses the hash value to determine whether a more detailed symbol by symbol comparison is required between a group of sequential symbols stored in the array and a target pattern stored in external storage. This is done by comparing the hash value with the indices of the target patterns in the external storage. If the more detailed comparison is indicated, a full comparison stage retrieves the relevant target pattern and compares the target pattern with the sequentially stored symbols in the array. To improve the determination of whether the detailed comparison is required, a confidence stage may be placed between the trigger stage and the full comparison stage. The confidence stage computes a hashing function value based on c sequential symbols in the array with c&#x2267;k. The hashing function value is then used to determine whether the more time consuming symbol by symbol comparison is needed.

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Ottawa, Canada

John F Pillar