Other

Pfg IP LLC

Irvine Sensors Corporation

Aprolase Development Co., LLC

Isc8 Inc.

John F Leon

Volkan H Ozguz

W Eric Boyd

Randolph Stuart Carlson

Keith D Gann

James S Yamaguchi

Angel Antonio Pepe

Randy Bindrup

Christian Krutzik

Robin Hansen

A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond 'through-via' accessible from at least the lower or second surface of the layer.

Wire bond through-via structure and method

A memory device such as a solid state memory device have a dual-hardware, secure erase feature. A memory controller operating in a memory controller domain provides general memory management and interface operons. Upon receipt of a trigger signal which may be received from a secure supervisor circuit, a separate processor element that is configured to directly access the raw memory cells in the device bypasses the memory controller domain and executes a separately provided secure erase operating system whereby the raw cell data may be erased and rewritten with a predetermined data pattern and whereby the erase operation at the raw cell level may be verified and reported to the user by the processor.

Solid state drive memory device comprising secure erase function

A high-speed processor core having a plurality of individual FPGA-based processing elements configured in a synchronous or asynchronous pipeline architecture with direct processor-to-memory interconnectivity that avoids the latency and bus contention delays of FPGAs using conventional bused memory. The high-speed processor core has one or more memory structures such as SDRAM or QDR electronic memory and is electrically coupled directly to one or more FPGAs using an access lead network to provide a pipelined set of FPGA-based processor elements for processing one or more predetermined operations such as one or more detection algorithms at line rates.

High-speed processor core comprising direct processor-to-memory connectivity

An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

Anti-tamper module

A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Field programmable gate array utilizing dedicated memory stacks in a vertical layer format

A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Field programmable gate array incorporating dedicated memory stacks

A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as mXN where m is the number of word width bits per memory chip and N is the number of memory chips.

Field programmable gate array with a variably wide word width memory

A common way for an adult to carry a baby is to cradle the baby in both arms, so that the baby's head is resting on one of the adult's shoulders. However, the baby may drool onto the adult. Also, thin adults with bony shoulders may cause discomfort to the baby's head. Such problems are solved by a combination baby pillow and drool guard that includes a shell stuffed with soft batting. A hole is arranged on the pad, so that it may be worn around the neck of the adult. The pad covers the shoulders and upper chest area of the adult to cushion the baby's head, and to protect the adult's clothing from the baby's drool. In a first embodiment, a pair of straps connect the opposite ends of the pad together when worn. In a second embodiment, a releasable joint extends between the hole and an edge of the pad for facilitating donning and removal. In a third embodiment, the pad includes a pair of wings extending from the sides for providing extra coverage on the adult's shoulders.

Baby pillow and drool guard

A self-draining cooking pot, such as a pasta pot, which facilitates the draining of liquid. A handle assembly includes a valve module which is readily-removable to facilitate cleaning, and a strainer to block the passage of food into the valve while permitting the flow of liquid. Included as part of the removable valve module is a sliding shaft with a resilient sealing member mounted on one end, and the sealing member is spring-biased against a valve seat. The handle assembly also includes a trigger lever for manual actuation of the valve. To prevent inadvertent draining of the pot, a lock-closed device engages the trigger lever until released by a pushbutton. To facilitate removal of the readily-removable valve module, a similar lock-open device is provided for the sliding shaft.

Self-draining cooking pot

A self-draining pot apparatus is set forth wherein a cooking vessel is formed with a pivotally and normally biased closure overlying, in a sealing arrangement, a plurality of openings enabling draining of fluid contained in said vessel during a cooking procedure. A removable screen oriented at an elevated position within said vessel enables steaming of various foods, such as vegetables, positionable on said screen. A finger lever positioned within a handle integrally secured to said vessel has secured thereto a flexible tether engaging said closure to enable opening of said closure and draining of the fluid within said vessel.

Growing community of inventors

Tryon, NC, United States of America

John F Leon