Micron Technology Incorporated

John F Kaeding

Owen R Fay

Chan H Yoo

Ashok Pachamuthu

Mark E Tuttle

Scott E Sills

Szu-Ying Ho

Richard J Hill

Shijian Luo

David K Hwang

Eiichi Nakano

John A Smythe

Glen H Walters

Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components.

Epitaxial single crystalline silicon growth for memory arrays

A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.

Tunable integrated millimeter wave antenna using laser ablation and/or fuses

A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

Use of pre-channeled materials for anisotropic conductors

A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.

Fabricated two-sided millimeter wave antenna using through-silicon-vias

Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material.

Semiconductor devices having integrated optical components

Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A method may include forming a set of walls on a surface of a substrate, the set of walls dividing the substrate into multiple sections, each of the multiple sections having at least one respective semiconductor device. The method may further include depositing a molding compound onto the substrate, the molding compound at least partially filling a space defined by the set of walls over each of the multiple sections and covering the respective semiconductor device of each of the multiple sections.

Sacrificial separators for wafer level encapsulating

Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.

Thrumold post package with reverse build up hybrid additive structure

Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.

Semiconductor device modules including a die electrically connected to posts and related methods

A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.

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Boise, ID, United States of America

John F Kaeding