Plessey Handel Und Investments A.g.

John F Dickson

Raymond Edward Oakley

John David Wilcock

A novel mode of operation of an array of MNOS memory transistors is provided which employs the punch through mode of erase and enables a single transistor memory cell to be used. It being arranged that all `bits` are written into the `1` state and bits are selectively erased to provide the required data pattern.

Semiconductor devices

A voltage multiplier circuit arrangement comprises a plurality of transistors connected a series between an input and an output of said arrangement, and first and second input lines arranged to have differential alternating voltage applied between them. Successive junctions between adjacent transistors are connected via respective capacitors to alternate ones of the first and second input lines. The control electrode (e.g. the gate or base electrode) of each one of said transistors is connected to a junction of two adjacent transistors, the latter being nearer to the output of said arrangement than is the one transistor. The junction is connected via one of the capacitors with the input line with which said one transistor is connected.

Voltage multiplier employing clock gated transistor chain

An MOST buffer circuit has a first normally non-conductive transistor in series with a second normally conductive transistor between earth and a main power supply. A normally discharged bootstrap capacitor is connected between the common connection point of the two transistors and the gate of the first transistor. In response to an input signal, the transistor is switched on, the transistors conduct in series, and the bootstrap capacitor charges. The transistor is then switched off, ceasing the series current and developing an output potential which approximates to that of the power supply.

Electrical integrated circuit chips

An information store comprising (a) a known latching circuit which comprises cross connected metal-oxide-silicon transistors and metal-nitride-oxide-silicon transistors and which is accommodated on an integrated circuit chip to which only earth and negative power is supplied, and (b) control means, positive potential for erasing being developed by applying earth and negative potentials selectively to input terminals of the control means, the control means comprising a resistor in series with a capacitor, and an output terminal at the junction of the resistor and capacitor.

Means for controlling the gate potential of MNOS transistors in a memory

A content addressable memory comprising for each storage element two non-volatile storage devices which can be non-destructively read and which are adapted to respectively store true and inverse information data, the two devices being interconnected in a manner which is such that information data stored by each device can be simultaneously compared with information data applied to the memory, the input of each of the two devices being connected to a separate terminal.

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Long Buckby, United Kingdom

John F Dickson