Nascentric, Inc.

Cadence Design Systems, Inc.

Silicon Metrics Corporation

Advanced Micro Devices Corporation

John F Croix

Curtis L Ratzlaff

Aaron Patzer

Stephen R King

Richard L Ratzel

Robert J Jones

Chanhee Oh

Robert Gonzalez

Ramon D Acosta

In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.

High speed memory simulation

In one embodiment, a method comprises partitioning a circuit description into a plurality of simulateable partitions. The partitioning is independent of a hierarchy specified in the circuit definition. The method also comprises sorting the plurality of simulateable partitions into one or more groups, wherein each simulateable partition included in a given group is equivalent to each other partition in the given group. Further, the method comprises simulating a first simulateable partition in the given group responsive to one or more input stimuli to the first simulateable partition. For each other simulateable partition in the given group that has approximately the same input stimuli as the first simulateable partition, the method still further comprises using a result of simulating the first simulateable partition as a result of the other simulateable partition.

Replicant simulation

In one embodiment, a method comprises partitioning a circuit description into simulateable partitions; sorting the simulateable partitions into classes wherein each simulateable partition included in a given class is equivalent to each other partition in the given class with a specified tolerance; associating a dynamic state machine with each class, wherein states of the dynamic state machine correspond to states reached by at least one simulateable partition in the given class during a simulation; during a simulation of the circuit description, the result of which is stored for user display: responsive to a current state in the dynamic state machine for a first simulateable partition in the given class and further responsive to input stimuli to the first simulateable partition, matching the one or more input stimuli to stimuli associated with a next state edge from the current state; and changing the current state of the first simulateable partition to a second state of the dynamic state machine indicated by the next state edge.

In one embodiment, a method comprises retaining at least a portion of simulation results corresponding to a first simulateable partition from a previous simulation time; and using the simulation results for a second simulateable partition (or the first simulateable partition) at a current simulation time if the second simulateable partition is equivalent to the first simulateable partition and one or more input stimuli to the second simulateable partition at the current simulation time are approximately the same as the input stimuli to the first simulateable partition at the previous simulation time. Computer accessible media storing instructions that implement the method are also contemplated.

Temporal replicant simulation

A system for analyzing a model of an electronic circuit, which includes at least one non-linear circuit element, includes a computer. The computer replaces the non-linear circuit element with a linearized circuit model that approximates a behavior of the non-linear circuit element. The computer also inserts into an element matrix a calculated value that corresponds to the linearized circuit model for a prescribed or desired time step. The computer further performs a numerical operation on the element matrix to effectively invert the element matrix.

Apparatus and methods for simulation of electronic circuitry

A system for analyzing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input, an output, and multiple controlled sources. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an associated value. Each of the multiple controlled sources has a current value derived from the input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an associated value. The computer is further configured to sweep the values for the input and output stimuli through a two sets of swept values, and to obtain an output current of the model of the circuit as a function of the swept values.

Apparatus and methods for cell models for timing and power analysis

In one embodiment, a system comprises a computer. The computer is configured to generate a plurality of partial sums corresponding to a first time point of a response on an interconnect, and generate the response at the first time point as a sum of the partial sums. The plurality of partial sums are a function of at least: one or more poles and residues of the interconnect and a time step; wherein at least a first partial sum of the plurality of partial sums is also a function of the first partial sum calculated for a second time point that precedes the first time point.

Apparatus and methods for interconnect simulation in electronic circuitry using non-uniform time step

A system for characterizing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input and output. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an output value. The computer is further configured to sweep the input and output values through a first and second set of swept values, and to characterize an output current of the model of the circuit as a function of the first and second swept values.

Apparatus and methods for current-based models for characterization of electronic circuitry

A system for characterizing an interconnect in an electrical circuit includes a computer. The computer calculates a set of terms, the set of terms derived from (i) a characteristic pole and a characteristic residue of the interconnect and (ii) a fixed time step used to describe a stimulus applied to the interconnect. The computer calculates a response of the interconnect to the stimulus by calculating a partial sum derived from the set of terms.

Apparatus and methods for interconnect characterization in electronic circuitry

Systems and methods are described for an encrypted compiler. A method includes generating a first sub-file of source code; then encrypting said first sub-file of source code; then writing said first sub-file of source code to a buffer; then reading a second sub-file of source code from said buffer; then decrypting said second sub-file of source code; and then compiling said second sub-file of source code.

Encrypted compiler

Systems and methods are described for rapid parameter passing. A method includes enumerating a set of parameters; providing an indication in a first set of arrays of whether to acquire from first program portion information associated with one or more parameters of the set of parameters, in response to a second program portion issuing a query t a third program portion for identifying the one or more parameters; populating a second et of arrays in an image of the first set of arrays with the information received from the first program portion associated with the one or more parameters, in response to a request from the second program portion; evaluating the third program portion by utilizing the information associated with the one or more parameters from the second set of arrays to derive an output from the third program portion for return to the second program portion; and conveying the output second program portion to the first program portion.

Rapid parameter passing between multiple program portions for efficient procedural interaction with minimum calls and/or call backs

Systems and methods are described for a circuit interconnect model compiler. A method includes providing extraction data from an interconnect; reading a dataset from said extraction data from said interconnect; reducing said dataset to form a model; evaluating said model for a set of conditions to obtain a solution; and writing said solution to an application. The systems and methods provide advantages in that the speed, reliability and accuracy of the design process are improved and the affect of circuit interconnects is taken into account.

Interconnect model compiler

According to a first model of an operation of circuitry, a first set of estimates of the operation is generated in response to a set of conditions, including a first estimate of the operation in response to a first condition. According to a second model of the operation, a second set of estimates of the operation is generated in response to the first condition and the first set. In response to a comparison between the first estimate and the second set, a subset of the first set is selected. According to the second model, an estimate of the operation is generated in response to a second condition and the selected subset.

Method and system for creating electronic circuitry

A reduced cell library includes substantially fewer cells than a complete cell library used to finalize the integrated circuit design. More particularly, each cell in the reduced cell library may be characterized by a first drive strength which is the same for each cell in the library. The reduced cell library can be used to evaluate the RTL description of an integrated circuit without incurring long synthesis delays. Large problems in the RTL description (with respect to one or more design goals) may be detected, and the RTL description may be modified to correct the problems.

Using a reduced cell library for preliminary synthesis to evaluate design

A reduced cell library includes substantially fewer cells than a complete cell library used to finalize the integrated circuit design. Having fewer cells reduces the number of options available to the synthesis tool for realizing a particular RTL description. Hence, the amount of time elapsing during a synthesis run using the reduced cell library may be substantially shorter than a corresponding synthesis run using a complete cell library. The reduced cell library can be used to evaluate the RTL description of an integrated circuit without incurring long synthesis delays. Large problems in the RTL description (with respect to one or more design goals) may be detected, and the RTL description may be modified to correct the problems. Once the RTL description of the integrated circuit substantially meets the design goals of the integrated circuit using the reduced cell library, synthesis using the complete cell library is initiated. The reduced cell library may be used to evaluate alternative RTL descriptions as well as cells proposed for addition into the complete cell library. The reduced cell library can be created even when the complete cell library is not yet available. In one embodiment, each of the cells in the reduced cell library is characterized by a uniform drive strength employed by all cells in the library. Attributes for the cells are generated using design goals, constraints, and assumptions.

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Austin, TX, United States of America

John F Croix