Zilog, Inc.

Psiquantum Corp.

Nantero, Inc.

Other

Cypress Semiconductor Corporation

American Semiconductor Corporation

Nanatero, Inc.

John Eugene Berg

Albert Wang

Ramakanth Alapati

Matteo Staffaroni

Gabriel J Mendoza

John A Smythe

Claude Louis Bertin

Thomas Rueckes

Alex Gyure

Damian Carver

Pete Manos

Yong Liang

Ann Melnichuk

Bernice L Kickel

John Elliott Ortmann, Jr

Irfan Rahim

Douglas R Hackler, Sr

Timothy K Carns

John A Ransom

A device includes a die stack including a first die including a quantum circuit and a second die including an electronic circuit. The second die and the first die face each other. A coupler is bonded to a first surface of the first die, an optical fiber is coupled to the coupler for coupling light from the optical fiber to the quantum circuit.

Photonic quantum computer assembly with a quantum computing die facing an electronic circuit die

A method of forming a film comprises growing, using a deposition system, at least a portion of the film and analyzing, using a RHEED instrument, the at least a portion of the film. Using a computer, data is acquired from the RHEED instrument that is indicative of a stoichiometry of the at least a portion of the film. Using the computer, adjustments to one or more process parameters of the deposition system are calculated to control stoichiometry of the film during subsequent deposition. Using the computer, instructions are transmitted to the deposition system to execute the adjustments of the one or more process parameters. Using the deposition system, the one or more process parameters are adjusted.

Fabrication of films having controlled stoichiometry using molecular beam epitaxy

A device includes a die stack including a first die including a quantum circuit and a second die including an electronic circuit. The second die and the first die face each other. The device also includes a first interconnect between the quantum circuit and the electronic circuit and a second interconnect between the quantum circuit and the electronic circuit.

Photonic quantum computer assembly

Techniques disclosed herein relate to devices that each include one or more photonic integrated circuits and/or one or more electronic integrated circuits. In one embodiment, a device includes a silicon substrate, a die stack bonded (e.g., fusion-bonded) on the silicon substrate, and a printed circuit board (PCB) bonded on the silicon substrate, where the PCB is electrically coupled to the die stack. The die stack includes a photonic integrated circuit (PIC) that includes a photonic integrated circuit, and an electronic integrated circuit (EIC) die that includes an electronic integrated circuit, where the EIC die and the PIC die are bonded face-to-face (e.g., by fusion bonding or hybrid bonding) such that the photonic integrated circuit and the electronic integrated circuit face each other. In some embodiments, the device also includes a plurality of optical fibers coupled to the photonic integrated circuit.

Quantum computing die assembly with thru-silicon vias

Photonic quantum computer assembly having dies with specific contact configuration and matched CTE

Quantum computing die assembly with thru-silicon vias and connected logic circuit

This interposer provides interconnections between stacked layers of circuits, which may include integrated circuits, PC boards, and hybrid substrates. Fabricated as an integrated circuit itself using readily available process steps, this interposer uses single and dual-damascene layers to increase the density of usable interconnections on both its top and bottom surfaces. Access from a top surface to a bottom surface is provided by conductive through-vias that may be placed at a high density. For even greater density, interconnections may be routed within silicon trenches, while damascene processing reduces the total number of steps required for fabrication. The described techniques may be used to create double-sided integrated circuits.

Triple-damascene interposer

Non-volatile field effect devices and circuits using same. A non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate have a corresponding terminal. An electromechanically-deflectable, nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal. The others of the source, drain and gate are directly connected to their corresponding terminals. The nanotube switching element is electromechanically-deflectable in response to electrical stimulation at two control terminals to create one of a non-volatile open and non-volatile closed electrical communication state between the one of the source, drain and gate and its corresponding terminal.

Non-volatile electromechanical field effect devices and circuits using same and methods of forming same

Non-volatile field effect devices and circuits using same. A non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate have a corresponding terminal. An electromechanically-deflectable, nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal. The others of the source, drain and gate are directly connected to their corresponding terminals. The nanotube switching element is electromechanically-deflectable in response to electrical stimulation at two control terminals to create one of a non-volatile open and non-volatile closed electrical communication state between the one of the source, drain and gate and its corresponding terminal. Under one embodiment, one of the two control terminals has a dielectric surface for contact with the nanotube switching element when creating a non-volatile open state. Under one embodiment, the source, drain and gate may be stimulated at any voltage level from ground to supply voltage, and wherein the two control terminals are stimulated at any voltage level from ground to a switching threshold voltage larger in magnitude than the supply voltage. Under one embodiment, the nanotube switching element includes an article made from nanofabric that is positioned between the two control terminals. Under one embodiment, one of the two control terminals is a release electrode for electrostatically pulling the nanotube article out of contact with the one of the source, drain and gate so as to form a non-volatile open state. Under one embodiment, the other of the two control terminals is a set electrode for electrostatically pulling the nanotube article into contact with the one of the source, drain and gate so as to form a non-volatile closed state.

A layout architecture for a programmable logic device comprising one or more adjacent metal lines, a first circuit, and a second circuit. The one or more adjacent metal lines may each comprise a critical path. The first circuit may be configured to present an input signal to each of the one or more adjacent metal lines in response to a configuration signal. The second circuit may be configured to (i) receive a signal from at least one of the one or more adjacent metal lines selected in response to the configuration signal and (ii) generate an output signal in response to the received signal.

Programmable number of metal lines and effective metal width along critical paths in a programmable logic device

Deposited dielectric layers for a semiconductor device are typically formed in a chemical vapor deposition. Often a hydrogen by-product is formed. Especially in a plasma enhanced chemical vapor deposition process, the hydrogen by-product can form free radicals that are introduced into the dielectric layers. The hydrogen free radicals can affect the stability of the threshold and breakdown voltage of MOSFET transistors. Deuterium introduced into the CVD chamber competes to enter the dielectric layer with the hydrogen. The deuterium prevents some of the hydrogen free radicals from entering the dielectric layer and thus increases MOSFET reliability.

Method of fabricating a MOS device

The present invention provides a method of forming a high quality thin oxide on a semiconductor body. A sacrificial oxide is formed on the semiconductor and then etched to eliminate the surface contamination of the semiconductor body. Then, an EEPROM oxide is formed following by an arsenic implant. Next the EEPROM oxide on the semiconductor body is then prepared by thin oxide growth. The thin oxide is preferably formed in a steam ambient. Subsequently, the oxide is annealed under nitrous oxide ambient using a combination of in-situ and RTP annealing process.

Method of fabricating a high quality thin oxide

The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.

Growing community of inventors

Palo Alto, CA, United States of America

John Eugene Berg