Rambus Inc.

Synopsys, Inc.

John Eric Linstadt

Frederick Abbott Ware

Kenneth Lee Wright

Scott C Best

Thomas J Giovannini

Thomas Vogelsang

Liji Gopalakrishnan

Ely K Tsern

Brent Steven Haukness

Craig Edward Hampel

Catherine Yuhjung Chen

Carl William Werner

Michael Raymond Miller

Torsten Partsch

Paul William Roukema

Stephen Magee

Steven Cameron Woo

David Geoffrey Stork

Christopher Haywood

Zhichao Lu

Patrick R Gill

Evan Lawrence Erickson

Catherine Chen

Yohan Usthavia Frans

Jun Y Kim

Trung Am Diep

Simon Li

Helena Handschuh

Venu Madhav Kuchibhotla

John Yan

Deepak Chandra Sekar

Hongzhong Zheng

Bohuslav Rychlik

James Edward Harris

Taeksang Song

J James Tringali

Mark D Kellam

Michael Alexander Hamburg

Hansel A Collins

Venu Madhav Kuchibholta

Thomas A Giovannini

A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is 'hybrid' in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.

Memory controller partitioning for hybrid memory system

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

Energy-efficient error-correction-detection storage

An apparatus and method for flexible metadata allocation and caching. In one embodiment of the method first and second requests are received from first and second applications, respectively, wherein the requests specify a reading of first and second data, respectively, from one or more memory devices. The circuit reads the first and second data in response to receiving the first and second requests. Receiving first and second metadata from the one or more memory devices in response to receiving the first and second requests. The first and second metadata correspond to the first and second data, respectively. The first and second data are equal in size, and the first and second metadata are unequal in size.

Flexible metadata allocation and caching

A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.

Memory system with cached memory module operations

A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

Memory system with error detection

Systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.

Integration of compression algorithms with error correction codes

A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

Memory system with multiple open rows per bank

A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the 'nominal' number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.

Partial array refresh timing

When writing a block (e.g., cache line) of data to a memory, error detection and correction (EDC) information (check) symbols are calculated. The block of data, a first portion of the check symbols, and metadata are all written concurrently at a first address. The remaining portion of the check symbols are written at a second, different from the first, address. When reading the block of data, a first read command accesses the block of data, the first portion of the check symbols, and the metadata from the first address. Only the first portion of the check symbols is used to determine a first number of errors (if any) in the accessed data. If the first number of errors meets a threshold number of errors, a second read command is issued to access the second portion of the check symbols.

Selectable multi-stage error detection and correction

Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

Energy efficient storage of error-correction-detection information

A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to access a memory. Memory interface circuitry couples to the memory. Message authentication circuitry performs a verification operation on the received request. Selective containment circuitry, during a containment mode of operation, (1) inhibits changes to the memory in response to the at least one command until completion of the verification operation, and (2) during performance of the verification operation, carries out at least one non-memory modifying sub-operation associated with the at least one command.

Integrity and data encryption (IDE) buffer device with low-latency containment mode

A multi-host processing system may access memory devices (e.g., memory modules, memory integrated circuits, etc.) via memory nodes having memory controllers. The memory controllers may be configured to use more than one error control scheme when accessing the same memory devices. The selection of the error control scheme may be made based on the interface receiving the memory transaction request. The selection of the error control scheme may be made based on information in the memory transaction request. The selection of the error control scheme may be made based on the fabric physical address and a lookup table or address range registers. The selection of the error control scheme may be made based on the memory device physical address and a lookup table or address range registers.

Dynamically configurable memory error control schemes

A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known 'bad' bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

Error coalescing

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

Growing community of inventors

Palo Alto, CA, United States of America

John Eric Linstadt