Texas Instruments Corporation

John Eric Kunz, Jr

Jonathan S Brodsky

Gianluca Boselli

Charvaka Duvvury

Akram Ali Salman

Farzan Farbiz

Aravind Chennimalai Appaswamy

Robert Steinhoff

Weibiao Zhang

Dening Wang

Liang Wang

Robert Matthew Mertens

An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.

ESD protection circuit with stacked ESD cells having parallel active shunt

An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.

Shut-off circuits for latched active ESD FET

An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.

Packaged device for detecting factory ESD events

An electrostatic discharge (ESD) protection circuit (FIG.A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a current path coupled between a first terminal and a second terminal. A second ESD cell has a current path coupled between the second terminal and a power supply terminal. A passive circuit is connected in parallel with one of the first and second ESD cells.

Programmable ESD protection circuit

An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD protection switch coupled between the bond pad and a common reference of the integrated circuit. At least one of a control bond pad and an enable logic circuit is coupled to a control terminal of the MEMS ESD protection switch.

Static MEMS switch for ESD protection

Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip of the probe. A first conductor is affixed to the attachment device so that the first conductor contacts the tip when the attachment device is attached to the tip of the probe. A second conductor extends between the first electrical conductor and a point external to the attachment device.

System and method for testing an electronic device

An apparatus comprises a first PFET including a first intrinsic body diode; an electrostatic discharge (ESD) subcircuit coupled to a source of the first PFET; a reverse bias voltage element, such as a zener diode, an anode of which is coupled to a gate of the first PFET; a second PFET having a source coupled to a cathode of the zener diode a capacitor coupled to a gate the second PFET; and a first resistor coupled to the gate of the second PFET. The apparatus can protect against both positive and negative electro static transient discharge events.

Low-impedance high-swing power supply with integrated high positive and negative DC voltage protection and electro-static discharge (ESD) protection

Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.

ESD protection validator, an ESD validation system and a method of validating ESD protection for an IC

A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.

System, an apparatus and a method for performing chip-level electrostatic discharge simulations

An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.

Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system

A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well, which touches source junction. Sourcehas further an ohmic (silicided) connection to contact. A finger-shaped diode () with its cathode () is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall ().

Guardwall structures for ESD protection

A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well. Further a finger-shaped diode () with its cathode () located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall ().

An equipment () for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator () and an on/off switch relay (). The relay is resistively connected by a first resistor () to the generator and by a second resistor () to the socket () for the device-under-test (); the relay is operable in a partially ionized ambient. A capacitor () is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor () is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 k&#x3a9; and 1 M&#x3a9;, preferably about 10 k&#x3a9;, several orders of magnitude greater than the on-resistance of the device-under-test.

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Allen, TX, United States of America

John Eric Kunz, Jr