Nortel Networks Corporation

Huawei Technologies Co., Limited

John Edward Vincent

Gary Michael Depelteau

Chang Hoon Lee

Louis-Philippe Hamelin

James Leslie Watchorn

Paul Alepin

Abdulaziz S Almulhem

Tony Huang

Olivier D'Arcy

Abdulaziz Almulhem

George Frank Irwin

David Anthony Fisher

Osama Bahgat

Peter Man-Kin Sinn

James C McLaughlin

Guy-Armand Kamendje Tchokobou

Melhem I Chaar

Peter Man Kin Sinn

Guy-Armand Kamendje Ichokobou

Paul Fong-Yan Hung

Benton Watson

Alan S J Chapman

Method and apparatus for process accelerator (PA) using configurable hardware accelerators is provided. The PA can include a plurality of processing elements (PEs). The PEs of the PA can be used to accelerate a process and/or one or more threads. PEs can include PE local memory which due to the memories' close physical proximity to the PE can result in reduced energy consumption. The plurality of PEs can be daisy-chain connected or DMA mode can be used to write the result of a PE directly into the PE local memory of another PE for further processing.

Method and apparatus for a configurable hardware accelerator

A computer system includes a first core including a first local cache and a second core including a second local cache. The first core and the second core are coupled through a remote link. A shared cache coupled to the first core and to the second core. The shared cache includes an ownership table that includes a plurality of entries indicating if a cache line is stored solely in the first local cache or solely in the second local cache. The remote link includes a first link between the first core and the shared cache and a second link between the second core and the shared cache.

System and methods for cache coherent system using ownership-based scheme

Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory

The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker circuit having a plurality of credit units associated with corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, and a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for a given period of time after the positive determination.

Handling Instruction Data and Shared resources in a Processor Having an Architecture Including a Pre-Execution Pipeline and a Resource and a Resource Tracker Circuit Based on Credit Availability

The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.

Method and apparatus for transaction based propagated clock-gating for low power design

A packet switch has a switching unit (SU) for switching packets between network links and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU. The SU is formed of different functional components interconnected by generic buses. The components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol. The communication between the components occurs by placing PDUs in bus frames that are passed from component to component. Information is exchanged between the components by adding information to or dropping information from the fields of the PDUs, or by concatenating new fields to the PDUs, as the frames pass from component to component. By using a generic bus to implement PDU-based interconnections within the SU, all the components are forced to support a common interface. Changes to the implementations of any component's interface can thus be accommodated by changing the PDU format as opposed to changing the interfaces of connected components. The new packet switch architecture decouples the components on the switch so that they can be upgraded or otherwise modified independently of one another.

Message based packet switch based on a common, generic bus medium for transport

A packet routing system is disclosed that allows for efficient transfers of IP streams from router to router with use of supertrunking. The router that receives an IP stream set for transmission on a supertrunk, individually inputs the IP packets, determines the logical output port corresponding to the IP stream, assigns each IP packet to a physical output port within the logical output port with use of a load balancing function, encapsulates each IP packet within a supertrunk header comprising an IP stream identifier and a packet sequence identifier and an IP header that has identical source and destination addresses as the original IP packet, and forwards the encapsulated packets to the receiving router via a plurality of physical links. The router that receives the encapsulated IP packets then re-orders the packets into the proper order with use of a sorting algorithm, removes the IP and supertrunk headers, and outputs an IP stream similar to that input to the original router.

Supertrunking for packet switching

A scheduling apparatus, that can be used within a supertrunking capable Internet Protocol (IP) Forwarding (IPF) node, allows for efficient scheduling of packets for servicing after the packets are sorted into their proper order. The scheduling apparatus has a point and serve mechanism, a round-robin mechanism, and a starvation mechanism, and is to be used in situations where an IPF node is sorting and outputting multiple numbers of data streams. The point and serve mechanism directs two supertrunk pointers to the front packets of the particular data streams that the incoming packet segments correspond. The round-robin mechanism rotates a round-robin pointer between the front packets corresponding to all the different data streams. The starvation mechanism flags a data stream as starving if no packets have been scheduled after a predetermined number of times in which the round-robin pointer has been directed at the particular stream. Since only a limited number of packets can be scheduled for servicing at a time and each packet is not necessarily ready to be scheduled, the scheduling apparatus prioritizes the scheduling of the packets. First attempting to schedule the front packets selected by the point and serve mechanism, then the starvation mechanism, and finally the round-robin mechanism.

Scheduling technique for delayed queue service

A packet routing system is disclosed that allows for efficient transfer of data flows from router to router with use of supertrunking. The router that receives a data flow inputs the packets of the data flow, determines the logical output port corresponding to the data flow, assigns the entire data flow to a physical output port within the logical output port with use of a load balancing function, encapsulates each packet within a Packet Forwarding Header (PFH) and a Rotator Information Unit (RIU) header that identifies the assigned physical output port, and outputs the encapsulated packets of the data flow to the assigned physical output port. The assigned physical output port removes the PFH and the RIU header from each packet and outputs the packets to a physical link. The router that receives the packets can treat the packets of the particular data flow like typical packets since all the packets of the same data flow traverse the same physical link resulting in no mis-ordering of packets.

Flow-level demultiplexing within routers

A virtual port scheduler is provided optionally for inclusion as part of a partitioned packet scheduler comprising a queue manager. The virtual port scheduler maintains a plurality of statuses for remote ports which do not have their own scheduling functionality. On the basis of those statuses, the virtual port scheduler determines which virtual port to service next.

Virtual port scheduler

Systems and methods for implementing ABR (available bit rate) flow control in ATM (asynchronous transfer mode switches are provided. A partitioned architecture a featuring standalone ABR processing subsystem advantageously allows components to be changed with little impact on the switch's overal design. Both end-to-end and VS/VD (virtual source/virtual destination) flow control systems are provided as are both configurations for switches which are either standalone or connected to a switching fabric.

Architecture for ABR processing within an ATM switch

A partitioned packet scheduler comprising a queue manager, an optionally connected rate shaper, and an optionally connected virtual port scheduler is provided. The packet scheduler is for use in a packet switch and has a very simple interface with the remainder of the switch consisting a channel for communicating buffer addresses and internal connection numbers. Very simple interfaces also exist between the queue manager and the rate shaper/virtual port scheduler thereby allowing independent design and update of these components to be performed.

Modular scalable packet scheduler with rate based shaping and virtual port scheduler

Methods and apparatus are described for translating identifiers that are used by computers to reference various entities such as data structures, external objects, or connections in a telecommunications network, from a bulkier less manageable format to a smaller more manageable format. Such translations are carried out to reduce the needless processing and memory demands that are made of a localized set of components when the large identifiers the set receives from other components include fields that none of the members of the set need to access. The invention is centerd around a two-stage look-up method wherein an inputted external identifier is divided into two parts. The first part of the inputted external identifier is used as an address into a first look-up table that contains base-addresses of a second look-up table. The second part of the inputted external identifier is used as an offset-address into the second look-up table. The offset-address and the base-address are combined to access the second look-up table, which contains all the internal identifiers. The invention can be easily scaled to handle a larger range of external identifiers, and a larger number of internal identifiers. The invention operates at a fast and predictable speed. Use of the invention also leads to a significant savings in memory costs.

Method and apparatus for full range translation of large external identifier to small internal identifier

A system and method for updating the congestion indication and no increase values in an resource management cell on an available bit rate connection in an asynchronous transfer mode network. The method determines a per port elastic allocatable rate as a function of a port's capacity, and the current high priority traffic rate. The values are set according to the underutilization or over utilization of the allocated elastic bandwidth.

Congestion indication/no increase (CI/NI) ABR flow control for ATM

A system and method for updating the explicit rate in an resource management cell on an available bit rate connection in an asynchronous transfer mode network. The method determines a per port elastic allocatable rate as a function of a port's capacity, and the current high priority traffic rate. A steering factor is used which is iteratively increased or decreased according to the underutilization or over utilization of the allocated elastic bandwidth.

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Ottawa, Canada

John Edward Vincent