Western Digital Technologies, Inc.

Micron Technology Incorporated

Quantum Corporation

Other

John Edward Maroney

Tridib Chakravarty

Mark Ish

Sanjay Subbarao

Christopher Joseph Bueb

Steven Scott Williams

Lyle E Adams

Johnny A Lam

David Matthew Springberg

Peter A Dickey

San A Phong

Paul A Suhler

Timothy J McCabe

Shaun Astarabadi

Thomas B Bolt

Musa Ibrahim Kakish

Charles Neumann

Edwin Dale Barnes

Thomas E Ludwig

Raoul Standt

Samuel Kevin Baughman

Christopher P Karr

Jan Jitze Krol

Hai Le

Varujan Sahakian

Hai Chi Le

A method for controlling aggregation for HRAM comprises a processing device, using a buffer manager, to receive instructions that include smaller-sized block write instructions from a host system. The processing device, using an aggregation engine, aggregates the smaller-sized block write instructions from the buffer manager into a plurality of larger-sized write instructions. The processing device issues a burst write instruction comprising the larger-sized write instructions to the memory component via the interface. The memory component can be HRAM and the interface can be a modified DDR-L5 interface for HRAM. Other embodiments are described herein.

Controlling aggregation for HRAM

A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

Multi-pass data programming in a memory sub-system having multiple dies and planes

A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Memory sub-system with multiple ports having single root virtualization

A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Logical-to-physical mapping of data groups with data locality

A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.

A processing device to perform operations including detecting a first host system connected to a first interface port of the plurality of interface ports of the memory device, the first host system is one of a plurality of host systems. Detecting a second host system connected to a second interface port of the plurality of interface ports, the second host system is one of the plurality of host systems. Assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV) and assigning a second subset of the plurality of VFs to the second host system using SR-IOV. Allocating a first corresponding range of logical block addresses (LBA) to each VF of the first subset of VFs and allocating a second corresponding range of LBAs to each VF of the second subset of VFs.

An indication of a capacity of a CMB elasticity buffer and an indication of a throughput of one or more memory components associated with the CMB elasticity buffer can be received. An amount of time for data at the CMB elasticity buffer to be transmitted to one or more memory components can be determined based on the capacity of the CMB elasticity buffer and the throughput of the one or more memory components. Write data can be transmitted from a host system to the CMB elasticity buffer based on the determined amount of time for data at the CMB elasticity buffer to be transmitted to the one or more memory components.

Providing information for a controller memory buffer elasticity status of a memory sub-system to a host system

An electrical board includes a ground layer, a power layer, a first signal layer, a top surface, first and second vias that extend substantially perpendicularly to the top surface through the ground layer, the power layer and the first signal layer, and one or more conductive traces disposed in the first signal layer, the one or more conductive traces lying between the first and second vias.

Inter-via conductive path routing

Systems and methods are disclosed for communicating data between a plurality of data storage devices. Multiple standalone data storage devices may be coupled to a data storage device docking station. A master data storage device may control the communication the communication of data between the standalone data storage devices. Slave data storage devices may communicated data based on one or more commands transmitted by the master data storage device.

Data storage device docking station

Systems and methods are disclosed for identifying disk drives and processing data access requests. A disk drive may be identified as an Advanced Host Controller Interface (AHCI) drive, a Non-Volatile Memory Express (NVME) drive, and/or an ATA packet interface (ATAPI) drive. Data access requests for the disk drive may be translated to NVME commands, AHCI commands, or ATAPI commands, based on whether the drive is identified as a NVME drive, an AHCI drive, and/or an ATAPI drive.

Identifying disk drives and processing data access requests

Systems and methods are disclosed for processing data access requests received from a direct access storage (DAS) interface and/or a network access storage (NAS) interface. The data access requests may be received from the DAS interface and the NAS interface substantially simultaneously. The data access requests may be scheduled based on priorities for the data access requests.

Processing data access requests from multiple interfaces for data storage devices

Systems and methods are disclosed for configuring multi-line serial computer expansion bus communication links. A controller for a data storage device may receive one or more signals indicative of bifurcation settings from a configuration component or a host bus adapter may provide one or more signals indicative of bifurcation settings to the controller. The controller may receive configuration data from the BIOS based on the one or more signals and may configure the multi-line serial computer expansion bus communication links based on the configuration data.

Configuring multi-line serial computer expansion bus communication links using bifurcation settings

The present invention relates to providing reliable power to a storage device. In one embodiment, the storage device employs dual external power supplies. The power supplies may both provide power to the storage device. Alternatively, the power supplies may provide power in different configurations. One power supply may be a primary supply providing all or a majority of power, while the other power supply may be a backup. The storage device may comprise high efficiency DC-to-DC converters to permit the use of lower power-rated external power supplies. A staggered startup procedure by the storage device may be implemented to manage peak power draw. The storage device may be further configured to load balance and power share between the external power supplies. In addition, the storage device is configured to monitor the status of the external power supplies and send a notification if one or more of the power supplies fails.

Growing community of inventors

Irvine, CA, United States of America

John Edward Maroney