Hewlett-packard Development Company, L.p.

Other

Compaq Computer Corporation, Inc.

University of California

Hewlett-packard Company

Compaq Information Technologies Group, L.p.

John Edward Larson

Robert A Lester

John MacLaren

Gary J Piccirillo

Jerome J Johnson

Michael J Collins

Michael P Moriarty

Christian H Post

Jeffery L Galloway

Gary W Thome

Eric Rose

Siamak Tavallaei

Tim W Majni

Anisha Anand

Paul A Santeler

Patrick Lee Ferguson

Jens K Ramsey

George D Megason

Brett D Roscoe

Ho M Lai

Benjamin H Clark

Phillip M Jones

Jeffrey C Stevens

Kenneth T Chin

Elizabeth Anne Richard

Sompong Paul Olarig

Jeffrey S Autor

Paul B Rawlins

Dan Fink

Bret D Roscoe

Thomas J Bonola

Kenneth A Jansen

William J Walker

Gary S Lynch

Charles N Shaver

Gary A Rogers

Paul J Broyles

James R Edwards

James R Reif

Todd J DeSchepper

Timothy R Zinsky

C Kevin Coffee

Wayne R Veltri

Sherry Larson

James Andre

Jim Blocker

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Error indication in a raid memory system

A wheel work chair has all the attributes and style of an office chair but is equipped with wheelchair-type supporting wheels The chair is height adjustable with the upper portion of the chair moving relative to the lower portion of the chair. Wheels connected to the upper portion of the chair move with the chair seat as the height of the chair is adjusted. Wheels connected to the lower portion of the chair remain on the ground as the height of the chair is adjusted. A static surface is provided on the arm of a height adjustable chair to support the weight of a user while that chair is being raised.

Wheeled work chair

A height adjustable structure comprises a base, a height adjustment column disposed above the base and supported thereon, and a table top or chair seat support disposed above the height adjustment column. Alternatively the height adjustable structure comprises two or more base sections, a height adjustment column disposed above each base section and supported thereon, and a table top or chair seat support disposed above the height adjustment columns. Each height adjustment column comprises a telescoping spring height adjustment lifting mechanism. The telescoping spring height adjustment lifting mechanism is typically a gas spring. Actuation mechanisms which actuate or unlock each lockable telescoping spring height adjustment lifting mechanism are used to allow the user to easily make height adjustments. The actuation mechanisms may extend above the table top. Connecting bars may be used to connect more than one actuation mechanism.

User height adjustable tables, support structures, and chairs

A pedestal has an S-shaped base and an upwardly extending member to support a furniture component. The S-shaped base provides an open leg envelope for persons seated at the pedestal. Workers at the pedestal's S-shaped table face opposite directions and enjoy independent work spaces.

Pedestals with S-shaped bases

A height adjustable chair has an upper portion that moves relative to a lower portion. Push-off arm rests are provided so that a person need not leave the chair to adjust the seat height upwardly. A seated person can transfer their body weight to the push-off arm rests supported directly by the stationary lower portion while the seat is being adjusted upwardly.

Height adjustable work chair

A transaction generator generates memory transactions identical to processor memory transactions to initialize, rebuild, and verify memory added or replaced during operation of a computer system configured for RAID memory. The transactions read and rewrite the correct value for replaced memory and write a known good value for added memory. Memory writes are verified by a read after the write transaction. The transaction generator is a state machine. A first counter is used for holding memory addresses of the transactions, automatically incrementing after each transaction. A second counter can throttle the generation of transactions by controlling the incrementation speed of the first counter. Transactions generated by the transaction generator have a transaction identifier, selected from a pool of available transaction identifiers. The transactions can complete out of order.

Transaction generator for initialization, rebuild, and verify of memory

Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

Technique for improving processor performance

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

Removable memory cartridge system for use with a server or other processor-based device

A technique for identifying the location of electrical components, such as memory cartridges which have been disposed on a substrate. More specifically, a connector configured to be coupled to a first substrate and configured to receive a second substrate, wherein the connector includes an identification device uniquely configured to provide location information and to electrically couple a plurality of location identification signals to the second substrate, the electrical signals being received from traces on the first substrate.

Technique for identifying multiple circuit components

Easy to assemble and disassemble tables have continuous frame members with at least two tapered sockets which support table legs. The continuous frame members are identical and thus can be used interchangeably as table bases and table top supports. The center of each taper within the continuous frame member is in the same position. Tapered sockets within each frame member insure that legs inserted into those sockets are parallel to one another. The parallelity of the table legs is further enhanced by inserting the other end of the table leg into a corresponding frame member in which the tapers are identically spaced. The tables are easy to assemble by inserting the tapered table legs into the 'self-holding' tapered sockets in the frame members. Easy disassembly of the tables is facilitated by quick release mechanisms which press the end of the leg seated in the socket to displace the leg from the socket.

Easily assembled and disassembled tables

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency

The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

Hot replace power control sequence logic

Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

Method for improving processor performance

Growing community of inventors

Houston, TX, United States of America

John Edward Larson